# US 12,010,796 B2 · Wiring substrate and method for manufacturing wiring substrate

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- Number: US 12,010,796 B2
- Document ID: US12010796B2
- Status: Granted
- Kind: B2
- Application number: 17/752,916
- Filed: 2022-05-25
- Published: 2022-12-01
- Granted: 2024-06-11
- Earliest claimed: 2021-05-28
- Assignees: Ibiden Co., Ltd.
- Applicants: Ibiden Co., Ltd.
- Inventors: Yoshinori Takenaka
- Web page: https://patentgrep.com/patent/US12010796B2

## CPC

- H05K 1/116: {Lands, clearance holes or other lay-out details concerning the surrounding of a via}
- H05K 1/0298: {Multilayer circuits}
- H05K 1/0373: {containing additives, e.g. fillers (H05K1/036 takes precedence)}
- H05K 3/4038: {Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence)}
- H05K 3/423: {characterised by electroplating method}
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H05K 1/0271: {Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion}
- H05K 2201/0154: Polyimide
- H05K 2201/068: wherein the coefficient of thermal expansion is important
- H05K 2201/096: Vertically aligned vias, holes or stacked vias
- H05K 2201/09827: Tapered, e.g. tapered hole, via or groove
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A wiring substrate includes an insulating layer including resin and filler particles, conductor layers including an upper-layer conductor layer and a lower-layer conductor layer such that the insulating layer is sandwiched between the upper-layer and lower-layer conductor layers, and a penetrating conductor formed in the insulating layer such that the penetrating conductor is penetrating through the insulating layer and connecting the upper-layer and lower-layer conductor layers. The penetrating conductor is formed such that the penetrating conductor has a first length which is the maximum width of the penetrating conductor in the direction orthogonal to the thickness direction of the wiring substrate and the first length is 25 μm or less, and the insulating layer is formed such that the maximum particle size of the filler particles in a region within the distance of 40% of the first length from the penetrating conductor is 20% or less of the first length.

## Claims

### Claim 1

A wiring substrate, comprising:
an insulating layer comprising resin and filler particles;
a plurality of conductor layers including an upper-layer conductor layer and a lower-layer conductor layer such that the insulating layer is sandwiched between the upper-layer conductor layer and the lower-layer conductor layer; and
a penetrating conductor formed in the insulating layer such that the penetrating conductor is penetrating through the insulating layer and connecting the upper-layer conductor layer and the lower-layer conductor layer,
wherein the penetrating conductor is formed such that the penetrating conductor has a first length which is a maximum width of the penetrating conductor in a direction orthogonal to a thickness direction of the wiring substrate and that the first length is 25 inn or less, and the insulating layer is formed such that a maximum particle size of the filler particles in a region within a distance of 40% of the first length from the penetrating conductor is 20% or less of the first length and that the insulating layer does not have the filler particles exposed at an interface between the insulating layer and the penetrating conductor.

### Claim 2 (depends on 1)

The wiring substrate according to claim 1, wherein the insulating layer is formed such that the insulating layer has a laser processed surface at the interface between the insulating layer and the penetrating conductor.

### Claim 3 (depends on 1)

The wiring substrate according to claim 1, wherein the insulating layer is formed such that a maximum particle size of the filler particles in the insulating layer is 20% or less of the first length.

### Claim 4 (depends on 1)

The wiring substrate according to claim 1, wherein the insulating layer is formed such that a volume content rate of the filler particles in the insulating layer is in a range of 30% to 80%.

### Claim 5 (depends on 1)

The wiring substrate according to claim 1, wherein the penetrating conductor is formed such that the penetrating conductor has the maximum width at a first end in the thickness direction of the wiring substrate and has a second length which a width in the direction orthogonal to the thickness direction of the wiring substrate at a second end on an opposite side with respect to the first end, and the insulating layer is formed such that a maximum particle size of the filler particles in the insulating layer is 20% or less of the second length.

### Claim 6 (depends on 1)

The wiring substrate according to claim 1, wherein one of the upper-layer conductor layer and the lower-layer conductor layer includes a conductor pad such that the conductor pad is integrally formed with the penetrating conductor, and the insulating layer is formed such that a maximum particle size of the filler particles in a region overlapping the conductor pad in a plan view is smaller than a distance from an outer edge of the conductor pad to an outer edge of the penetrating conductor in a plan view.

### Claim 7 (depends on 2)

The wiring substrate according to claim 2, wherein the insulating layer is formed such that a maximum particle size of the filler particles in the insulating layer is 20% or less of the first length.

### Claim 8 (depends on 2)

The wiring substrate according to claim 2, wherein the insulating layer is formed such that a volume content rate of the filler particles in the insulating layer is in a range of 30% to 80%.

### Claim 9 (depends on 2)

The wiring substrate according to claim 2, wherein the penetrating conductor is formed such that the penetrating conductor has the maximum width at a first end in the thickness direction of the wiring substrate and has a second length which a width in the direction orthogonal to the thickness direction of the wiring substrate at a second end on an opposite side with respect to the first end, and the insulating layer is formed such that a maximum particle size of the filler particles in the insulating layer is 20% or less of the second length.

### Claim 10 (depends on 2)

The wiring substrate according to claim 2, wherein one of the upper-layer conductor layer and the lower-layer conductor layer includes a conductor pad such that the conductor pad is integrally formed with the penetrating conductor, and the insulating layer is formed such that a maximum particle size of the filler particles in a region overlapping the conductor pad in a plan view is smaller than a distance from an outer edge of the conductor pad to an outer edge of the penetrating conductor in a plan view.

### Claim 11 (depends on 3)

The wiring substrate according to claim 3, wherein the insulating layer is formed such that a volume content rate of the filler particles in the insulating layer is in a range of 30% to 80%.

### Claim 12 (depends on 3)

The wiring substrate according to claim 3, wherein the penetrating conductor is formed such that the penetrating conductor has the maximum width at a first end in the thickness direction of the wiring substrate and has a second length which a width in the direction orthogonal to the thickness direction of the wiring substrate at a second end on an opposite side with respect to the first end, and the insulating layer is formed such that a maximum particle size of the filler particles in the insulating layer is 20% or less of the second length.

### Claim 13 (depends on 3)

The wiring substrate according to claim 3, wherein one of the upper-layer conductor layer and the lower-layer conductor layer includes a conductor pad such that the conductor pad is integrally formed with the penetrating conductor, and the insulating layer is formed such that a maximum particle size of the filler particles in a region overlapping the conductor pad in a plan view is smaller than a distance from an outer edge of the conductor pad to an outer edge of the penetrating conductor in a plan view.

### Claim 14 (depends on 4)

The wiring substrate according to claim 4, wherein the penetrating conductor is formed such that the penetrating conductor has the maximum width at a first end in the thickness direction of the wiring substrate and has a second length which a width in the direction orthogonal to the thickness direction of the wiring substrate at a second end on an opposite side with respect to the first end, and the insulating layer is formed such that a maximum particle size of the filler particles in the insulating layer is 20% or less of the second length.

### Claim 15 (depends on 4)

The wiring substrate according to claim 4, wherein one of the upper-layer conductor layer and the lower-layer conductor layer includes a conductor pad such that the conductor pad is integrally formed with the penetrating conductor, and the insulating layer is formed such that a maximum particle size of the filler particles in a region overlapping the conductor pad in a plan view is smaller than a distance from an outer edge of the conductor pad to an outer edge of the penetrating conductor in a plan view.

### Claim 16 (depends on 5)

The wiring substrate according to claim 5, wherein one of the upper-layer conductor layer and the lower-layer conductor layer includes a conductor pad such that the conductor pad is integrally formed with the penetrating conductor, and the insulating layer is formed such that a maximum particle size of the filler particles in a region overlapping the conductor pad in a plan view is smaller than a distance from an outer edge of the conductor pad to an outer edge of the penetrating conductor in a plan view.

### Claim 17 (depends on 7)

The wiring substrate according to claim 7, wherein the insulating layer is formed such that a volume content rate of the filler particles in the insulating layer is in a range of 30% to 80%.