# US 12,010,447 B2 · Dynamic vision sensor architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,010,447 B2 - Document ID: US12010447B2 - Status: Granted - Kind: B2 - Application number: 18/206,634 - Filed: 2023-06-07 - Published: 2023-10-12 - Granted: 2024-06-11 - Earliest claimed: 2016-12-30 - Assignees: Sony Advanced Visual Sensing AG - Applicants: Sony Advanced Visual Sensing AG - Inventors: Raphael Berner; Christian Brändli - Web page: https://patentgrep.com/patent/US12010447B2 ## CPC - H04N 25/767: Horizontal readout lines, multiplexers or registers - H10F 39/8033: {Photosensitive area} - H04N 25/44: by partially reading an SSIS array - H04N 25/47: Image sensors with pixel address output; Event-driven image sensors; Selection of pixels to be read out based on image data - H04N 25/573: {the logarithmic type} - H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components - H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters - H04N 25/778: comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract A dynamic vision sensor (DVS) or change detection sensor reacts to changes in light intensity and in this way monitors how a scene changes. This disclosure covers both single pixel and array architectures. The DVS may contain one pixel or 2-dimensional or 1-dimensional array of pixels. The change of intensities registered by pixels are compared, and pixel addresses where the change is positive or negative are recorded and processed. Analyzing frames based on just three values for pixels, increase, decrease or unchanged, the proposed DVS can process visual information much faster than traditional computer vision systems, which correlate multi-bit color or gray level pixel values between successive frames. ## Claims ### Claim 1 An imaging device comprising: a photoelectric conversion region; first circuitry coupled to the photoelectric conversion region; a first capacitor coupled to the first circuitry; comparison circuitry coupled to the first capacitor that compares a first signal based on an output from the photoelectric conversion region to both a first reference voltage and a second reference voltage selectively and that includes a first terminal that receives the first signal and a second terminal that receives the first reference voltage and the second reference voltage selectively, and reset circuitry that resets the first capacitor based on an output from the comparison circuitry and a global reset signal. ### Claim 2 (depends on 1) The device as claimed in claim 1, wherein the output from the comparison circuitry includes ON event signals and OFF event signals. ### Claim 3 (depends on 1) The device as claimed in claim 1, wherein the comparison circuitry outputs ON event signals during ON comparison phases and OFF event signals during OFF comparison phases. ### Claim 4 (depends on 1) The device as claimed in claim 1, wherein the first reference voltage is coupled to the second terminal during ON comparison phases. ### Claim 5 (depends on 4) The device as claimed in claim 4, wherein the second reference voltage is coupled to the second terminal during OFF comparison phases. ### Claim 6 (depends on 5) The device as claimed in claim 5, wherein the second terminal receives a third reference voltage during reset phases. ### Claim 7 (depends on 6) The device as claimed in claim 6, further comprising controller circuitry that controls the switching of the first reference voltage, the second reference voltage and third reference voltage. ### Claim 8 (depends on 1) The device as claimed in claim 1, wherein the reset circuitry includes a logical AND operator. ### Claim 9 (depends on 1) The device as claimed in claim 1, further comprising memory circuitry that stores the output from the comparison circuitry. ### Claim 10 (depends on 9) The device as claimed in claim 9, further comprising readout circuitry that controls the memory circuitry to read the output from the comparison circuitry. ### Claim 11 (depends on 1) The device as claimed in claim 1, wherein the first circuitry includes logarithm circuit. ### Claim 12 An imaging device comprising an array of pixels, wherein each of the pixels includes: a photoelectric conversion region; first circuitry coupled to the photoelectric conversion region; a first capacitor coupled to the first circuitry; comparison circuitry coupled to the first capacitor that compares a first signal based on an output from the photoelectric conversion region to both a first reference voltage and a second reference voltage selectively and that includes a first terminal that receives the first signal and a second terminal that receives the first reference voltage and the second reference voltage selectively, and reset circuitry that resets the first capacitor based on an output from the comparison circuitry and a global reset signal. ### Claim 13 (depends on 12) The device as claimed in claim 12, wherein the output from the comparison circuitry includes ON event signals and OFF event signals. ### Claim 14 (depends on 12) The device as claimed in claim 12, wherein the comparison circuitry outputs ON event signals during ON comparison phases and OFF event signals during OFF comparison phases. ### Claim 15 (depends on 12) The device as claimed in claim 12, wherein the first reference voltage is coupled to the second terminal during ON comparison phases and the second reference voltage is coupled to the second terminal during OFF comparison phases. ### Claim 16 (depends on 15) The device as claimed in claim 15, wherein the second terminal receives a third reference voltage during reset phases. ### Claim 17 (depends on 16) The device as claimed in claim 16, further comprising controller circuitry that controls the switching of the first reference voltage, the second reference voltage and third reference voltage. ### Claim 18 (depends on 12) The device as claimed in claim 12, wherein the reset circuitry includes a logical AND operator. ### Claim 19 (depends on 12) The device as claimed in claim 12, further comprising memory circuitry that stores the output from the comparison circuitry and readout circuitry that controls the memory circuitry to read the output from the comparison circuitry. ### Claim 20 (depends on 12) The device as claimed in claim 12, wherein the first circuitry includes logarithm circuit.