# US 12,010,033 B2 · On chip router > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,010,033 B2 - Document ID: US12010033B2 - Status: Granted - Kind: B2 - Application number: 17/997,085 - Filed: 2021-04-26 - Published: 2023-06-29 - Granted: 2024-06-11 - Earliest claimed: 2020-04-28 - Assignees: Cogniscience Limited - Applicants: Cogniscience Limited - Inventors: Steve Furber; Gengting Liu - Web page: https://patentgrep.com/patent/US12010033B2 ## CPC - H04L 47/32: by discarding or delaying data units, e.g. packets or frames - H04L 47/129: at the destination endpoint, e.g. reservation of terminal resources or buffer space - H04L 49/9063: {Intermediate storage in different physical parts of a node or terminal} - G06N 3/063: using electronic means - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract There is disclosed a router for routing data on a computing chip comprising a plurality of processing elements, the router comprising: a packet processing pipeline; a dropped packet buffer; and one or more circuits configured to: determine that a data packet in the packet processing pipeline is to be dropped; move the data packet that is to be dropped from the packet processing pipeline to the dropped packet buffer; and re-insert the dropped data packet from the dropped packet buffer into the packet processing pipeline for re-processing. ## Claims ### Claim 1 A router for routing data on a computing chip comprising a plurality of processing elements, the router comprising: a packet processing pipeline; and a hardware mechanism for packet dropping and re-insertion, fully within the router, the hardware mechanism comprising: a dropped packet buffer; and one or more circuits configured to: determine that a data packet in the packet processing pipeline is to be dropped; move the data packet that is to be dropped from the packet processing pipeline to the dropped packet buffer; and re-insert, with the one or more circuits within the router, the dropped data packet from the dropped packet buffer into the packet processing pipeline for re-processing. ### Claim 2 (depends on 1) The router of claim 1, wherein the one or more circuits are configured to determine that a data packet in the packet processing pipeline is to be dropped based upon a signal indicating that a destination of the data packet is unable to receive the data packet. ### Claim 3 (depends on 1) The router of claim 1, wherein the packet processing pipeline further comprises an out-of-order packet buffer and wherein the one or more circuits are configured to move the data packet that is to be dropped from the out-of-order packet buffer to the dropped packet buffer. ### Claim 4 (depends on 3) The router of claim 3, wherein the one or more circuits are further configured to: select a data packet for processing by the packet processing pipeline; determine one or more destinations of the data packet; determine that a destination of the one or more destinations of the data packet is unable to receive the data packet; and move the data packet to the out-of-order packet buffer. ### Claim 5 (depends on 3) The router of claim 3, wherein the data packet that is to be dropped is the oldest data packet in the out-of-order packet buffer. ### Claim 6 (depends on 1) The router of claim 1, wherein the one or more circuits are configured to determine that a data packet in the packet processing pipeline is to be dropped based upon the expiration of a timer. ### Claim 7 (depends on 1) The router of claim 1, wherein the one or more circuits are configured to re-insert the dropped data packet from the dropped packet buffer into the packet processing pipeline for re-processing based upon a timer. ### Claim 8 (depends on 1) The router of claim 1, wherein the one or more circuits are configured to re-insert the dropped data packet from the dropped packet buffer into the packet processing pipeline for re-processing based upon a load of the packet processing pipeline. ### Claim 9 (depends on 1) The router of claim 1, wherein the router is configured to provide a software-based packet offload operation to remove a data packet stored in the dropped packet buffer for re-processing of the data packet outside of the router. ### Claim 10 (depends on 1) The router of claim 1, wherein the packet processing pipeline is configured to process multi-cast data packets. ### Claim 11 (depends on 1) The router of claim 1, wherein the dropped packet buffer is configured to store a plurality of dropped data packets. ### Claim 12 (depends on 1) The router of claim 1, wherein the dropped packet buffer comprises one or more SRAM modules. ### Claim 13 (depends on 1) The router of claim 1, wherein the computing chip is a neuromorphic chip. ### Claim 14 A method of routing data with a router on a computing chip comprising a plurality of processing elements, the router comprising a packet processing pipeline, a dropped packet buffer, and one or more circuits, the method comprising: determining, by the one or circuits of the router, that a data packet in the packet processing pipeline is to be dropped; moving, by the one or more circuits of the router, the data packet that is to be dropped from the packet processing pipeline to the dropped packet buffer within the router; and re-inserting, by the one or more circuits of the router, the dropped data packet from the dropped packet buffer into the packet processing pipeline for re-processing without transmission of the dropped packet to a monitor processor and re-transmission to the router. ### Claim 15 (depends on 14) The method of claim 14, wherein determining that a data packet in the packet processing pipeline is to be dropped is based upon a signal indicating that a destination of the data packet is unable to receive the data packet. ### Claim 16 (depends on 14) The method of claim 14, further comprising moving the data packet that is to be dropped from an out-of-order packet buffer to the dropped packet buffer. ### Claim 17 (depends on 16) The method of claim 16, further comprising: selecting a data packet for processing by the packet processing pipeline; determining one or more destinations of the data packet; determining that a destination of the one or more destinations of the data packet is unable to receive the data packet; and moving the data packet to the out-of-order packet buffer. ### Claim 18 (depends on 16) The method of claim 16, wherein the data packet that is to be dropped is the oldest data packet in the out-of-order packet buffer. ### Claim 19 (depends on 14) The method of claim 14, wherein determining that a data packet in the packet processing pipeline is to be dropped is based upon the expiration of a timer. ### Claim 20 (depends on 14) The method of claim 14, wherein re-inserting the dropped data packet from the dropped packet buffer into the packet processing pipeline for re-processing is based upon a load of the packet processing pipeline. ### Claim 21 (depends on 14) The method of claim 14, further comprising removing a data packet stored in the dropped packet buffer in response to a software-based packet offload operation. ### Claim 22 (depends on 14) The method of claim 14, wherein the packet processing pipeline is configured to process multi-cast data packets. ### Claim 23 (depends on 14) The method of claim 14, wherein the dropped packet buffer is configured to store a plurality of dropped data packets. ### Claim 24 (depends on 14) The method of claim 14, wherein the dropped packet buffer comprises one or more SRAM modules. ### Claim 25 (depends on 14) The method of claim 14, wherein the computing chip is a neuromorphic chip.