# US 12,009,943 B2 · Field bus driver circuit

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- Number: US 12,009,943 B2
- Document ID: US12009943B2
- Status: Granted
- Kind: B2
- Application number: 17/468,327
- Filed: 2021-09-07
- Published: 2022-04-21
- Granted: 2024-06-11
- Earliest claimed: 2020-10-15
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Jens Repp; Thorsten Hinderer; Maximilian Mangst; Eric Pihet
- Web page: https://patentgrep.com/patent/US12009943B2

## CPC

- H04L 12/40006: {Architecture of a communication node (current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90)}
- H03K 5/01: Shaping pulses (discrimination against noise or interference H03K5/125)
- H03K 17/102: {in field-effect transistor switches}
- H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor}
- H03K 17/6872: {using complementary field-effect transistors}
- H03K 2005/00013: {Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse}
- H04L 2012/40215: {Controller Area Network CAN}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A transmitter circuit for a field bus driver includes a first bus terminal and a second bus terminal for connecting a first bus line and, respectively, a second bus line. The transmitter circuit further includes a first supply terminal for receiving a supply voltage and second supply terminal for receiving a reference voltage, a first switching circuit coupled between the first supply terminal and the first bus terminal, and a second switching circuit coupled between the second bus terminal and the second supply terminal. The first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor. Further, the transmitter circuit comprises control circuitry configured to generate first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor based on a transmit signal.

## Claims

### Claim 1

A transmitter circuit for a field bus driver, the transmitter circuit comprising:
a first bus terminal and a second bus terminal for connecting a first bus line and, respectively, a second bus line;
a first supply terminal for receiving a supply voltage and a second supply terminal for receiving a reference voltage; and
a first switching circuit coupled between the first supply terminal and the first bus terminal, and a second switching circuit coupled between the second bus terminal and the second supply terminal;
wherein the first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor; and
wherein the transmitter circuit further comprises control circuitry configured to generate first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor based on a transmit signal,
wherein the control circuitry is configured to generate the second drive signals such that:
the second transistor and the fourth transistor are switched on in response to the transmit signal indicating a transition from a recessive to a dominant bus state, and
the second transistor and the fourth transistor are switched off when the transmit signal indicates a recessive bus state and a specific first delay time has lapsed since the transmit signal indicating a transition from a dominant to a recessive bus state.

### Claim 2 (depends on 1)

The transmitter circuit of claim 1,
wherein the first switching circuit includes a first diode element coupled to the second transistor and the second switching circuit includes a second diode element coupled to the fourth transistor.

### Claim 3 (depends on 2)

The transmitter circuit of claim 2,
wherein the first diode element and the second diode element each comprise a MOS-transistor having a gate electrode connected to a source electrode.

### Claim 4 (depends on 2)

The transmitter circuit of claim 2,
wherein the first diode element and the second diode element are formed by intrinsic drain-bulk-diodes of MOS-transistors.

### Claim 5 (depends on 1)

The transmitter circuit of claim 1, further comprising:
a fifth transistor coupled between the first bus terminal and the first supply terminal; and
a sixth transistor coupled between the second bus terminal and the second supply terminal.

### Claim 6 (depends on 5)

The transmitter circuit of claim 5,
wherein the control circuitry is configured to generate third drive signals for the fifth transistor and the sixth transistor such that the fifth transistor and the sixth transistor switch on and off in synchronization with the first transistor and the third transistor.

### Claim 7 (depends on 6)

The transmitter circuit of claim 6,
wherein the control circuitry is configured to generate third drive signals for the fifth transistor and the sixth transistor such that the fifth transistor and the sixth transistor switch on a predetermined time lag after the first transistor and the third transistor.

### Claim 8 (depends on 1)

The transmitter circuit of claim 1,
wherein the control circuitry is configured to delay the first drive signals for the first transistor and the third transistor such that the first transistor and the third transistor switch on after the second transistor and, respectively, the fourth transistor.

### Claim 9 (depends on 1)

The transmitter circuit of claim 1,
wherein the first transistor and the third transistor both comprise a plurality of transistor cells and/or
wherein the second transistor and the fourth transistor both comprise a plurality of transistor cells.

### Claim 10 (depends on 1)

The transmitter circuit of claim 1, further comprising:
a common mode voltage source coupled to the first bus terminal and the second bus terminal via a first resistor and, respectively, a second resistor; and
a compensation circuit configured to connect the common mode voltage source, or another common mode voltage source, with both, the first bus terminal and the second bus terminal, during a switching process of the third transistor and the fourth transistor to bypass the first resistor and the second resistor.

### Claim 11 (depends on 1)

The transmitter circuit of claim 1,
wherein the control circuitry includes a control circuit configured to switch the second transistor and the fourth transistor on and off, and further configured to:
generate, during a switch-on process of the second transistor and the fourth transistor, a compensation current equal to a gate current of the second and the fourth transistors, and inject the compensation current into a load current path of the corresponding second and fourth transistor.

### Claim 12 (depends on 11)

The transmitter circuit of claim 11,
wherein the control circuit includes a plurality of current mirrors configured to mirror the gate current of the second and the fourth transistors during the switch-on process and generate the compensation current based on the mirrored gate currents.

### Claim 13

A method for operating a transmitter circuit for a field bus driver that comprises:
a first bus terminal and a second bus terminal for connecting a first bus line and, respectively, a second bus line;
a first supply terminal for receiving a supply voltage and second supply terminal for receiving a reference voltage; and
a first switching circuit coupled between the first supply terminal and the first bus terminal, and a second switching circuit coupled between the second bus terminal and the second supply terminal;
wherein the first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor; and
wherein the method comprises:
generating first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor based on a transmit signal, wherein the second drive signals are generated such that:
the second transistor and the fourth transistor are switched on in response to the transmit signal indicating a transition from a recessive to a dominant bus state, and
the second transistor and the fourth transistor are switched off when the transmit signal indicates a recessive bus state and a specific first delay time has lapsed since the transmit signal indicating a transition from a dominant to a recessive bus state.