# US 12,009,850 B2 · Reconfigurable amplifier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,850 B2 - Document ID: US12009850B2 - Status: Granted - Kind: B2 - Application number: 18/317,011 - Filed: 2023-05-12 - Published: 2023-09-07 - Granted: 2024-06-11 - Earliest claimed: 2021-08-17 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Janakiram Sankaranarayanan; Jun Tan; Lai Kan Leung; Timothy Donald Gathman; Mehmet Ipek; Ojas Choksi - Web page: https://patentgrep.com/patent/US12009850B2 ## CPC - H03F 3/195: in integrated circuits - H04B 1/18: Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) - H03F 1/0211: {with control of the supply voltage or current} - H03F 1/0261: {with control of the polarisation voltage or current, e.g. gliding Class A} - H03F 1/223: {with MOSFET's} - H03F 3/19: with semiconductor devices only - H03F 3/3022: {CMOS common source output SEPP amplifiers (H03F3/3008 takes precedence)} - H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal - H03F 2200/129: there being a feedback over the complete amplifier - H03F 2200/144: the feedback circuit of the amplifier stage comprising a passive resistor and passive capacitor - H03F 2200/147: the feedback circuit comprising a series resonance circuit - H03F 2200/294: the amplifier being a low noise amplifier [LNA] - H03F 2200/42: the input to the amplifier being made by capacitive coupling means - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2200/48: the output of the amplifier being coupled out by a capacitor - H03F 2200/511: Many discrete supply voltages or currents or voltage levels can be chosen by a control signal in an IC-block amplifier circuit - H03F 2200/519: the bias or supply voltage or current of the drain side of a FET amplifier being controlled to be on or off by a switch - H03F 2203/30084: the pull circuit of the SEPP amplifier being a cascode circuit - H03F 2203/30117: the push circuit of the SEPP amplifier being a cascode circuit - H03F 2203/7227: the gated amplifier being switched on or off by a switch in the supply circuit of the amplifier - H03F: AMPLIFIERS - H04B: TRANSMISSION ## Abstract An amplifying circuit includes a first reconfigurable amplifier configured to selectively operate in a cascode mode or a non-cascode mode, wherein an input of the first reconfigurable amplifier is coupled to a first input of the amplifying circuit, and an output of the first reconfigurable amplifier is coupled to an output of the amplifying circuit. The amplifying circuit also includes a second reconfigurable amplifier configured to selectively operate in the cascode mode or the non-cascode mode, wherein an input of the second reconfigurable amplifier is coupled to a second input of the amplifying circuit, and an output of the second reconfigurable amplifier is coupled to the output of the amplifying circuit. ## Claims ### Claim 1 An apparatus, comprising: an amplifying circuit, comprising: a first reconfigurable amplifier configured to selectively operate in a cascode mode or a non-cascode mode, wherein an input of the first reconfigurable amplifier is coupled to a first input of the amplifying circuit, and an output of the first reconfigurable amplifier is coupled to an output of the amplifying circuit; and a second reconfigurable amplifier configured to selectively operate in the cascode mode or the non-cascode mode, wherein an input of the second reconfigurable amplifier is coupled to a second input of the amplifying circuit, and an output of the second reconfigurable amplifier is coupled to the output of the amplifying circuit; and a controller coupled to the first reconfigurable amplifier and the second reconfigurable amplifier, wherein the controller is configured to: in a combining mode, cause the first reconfigurable amplifier to operate in the cascode mode and the second reconfigurable amplifier to operate in the cascode mode; and in a first multiplexing mode, cause the first reconfigurable amplifier to operate in the non-cascode mode and turn off the second reconfigurable amplifier. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the controller is configured to, in a second multiplexing mode, cause the second reconfigurable amplifier to operate in the non-cascode mode and turn off the first reconfigurable amplifier. ### Claim 3 (depends on 1) The apparatus of claim 1, further comprising: a first mixer coupled to the output of the amplifying circuit; and a second mixer coupled to the output of the amplifying circuit. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first reconfigurable amplifier comprises: a first transistor having a gate coupled to the input of the first reconfigurable amplifier, and a source coupled to a ground; a second transistor having a source coupled to a drain of the first transistor, and a drain coupled to the output of the first reconfigurable amplifier; a first load coupled to the output of the first reconfigurable amplifier; and a first gate control circuit coupled to a gate of the second transistor, wherein the first gate control circuit is configured to: in the cascode mode, bias the second transistor in a saturation region; and in the non-cascode mode, bias the second transistor in a triode region. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the first reconfigurable amplifier further comprises: a supply control circuit, wherein the first load is coupled between the output of the first reconfigurable amplifier and the supply control circuit, and wherein the supply control circuit is configured to: output a first supply voltage to the first load in the cascode mode; and output a second supply voltage to the first load in the non-cascode mode, wherein the first supply voltage is higher than the second supply voltage. ### Claim 6 (depends on 4) The apparatus of claim 4, wherein the second reconfigurable amplifier comprises: a third transistor having a gate coupled to the input of the second reconfigurable amplifier, and a source coupled to the ground; a fourth transistor having a source coupled to a drain of the third transistor, and a drain coupled to the output of the second reconfigurable amplifier; a second load coupled to the output of the second reconfigurable amplifier; and a second gate control circuit coupled to a gate of the fourth transistor, wherein the second gate control circuit is configured to: in the cascode mode, bias the fourth transistor in the saturation region; and in the non-cascode mode, bias the fourth transistor in the triode region. ### Claim 7 A method of amplification using a first reconfigurable amplifier and a second reconfigurable amplifier, wherein each of the first reconfigurable amplifier and the second reconfigurable amplifier is configured to selectively operate in a cascode mode or a non-cascode mode, the method comprising: in a combining mode, amplifying a first signal using the first reconfigurable amplifier operating in the cascode mode to obtain an amplified first signal; amplifying a second signal using the second reconfigurable amplifier operating in the cascode mode to obtain an amplified second signal; and combining the amplified first signal and the amplified second signal; and in a first multiplexing mode; turning off the second reconfigurable amplifier; and amplifying the first signal using the first reconfigurable amplifier operating in the non-cascode mode to obtain the amplified first signal. ### Claim 8 (depends on 7) The method of claim 7, further comprising: in a second multiplexing mode, turning off the first reconfigurable amplifier; and amplifying the second signal using second reconfigurable amplifier operating in the non-cascode mode to obtain the amplified second signal.