# US 12,009,843 B2 · Matrix compression accelerator system and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,843 B2 - Document ID: US12009843B2 - Status: Granted - Kind: B2 - Application number: 17/195,703 - Filed: 2021-03-09 - Published: 2021-06-24 - Granted: 2024-06-11 - Earliest claimed: 2017-02-24 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Arthur John Redfern; Dan Wang - Web page: https://patentgrep.com/patent/US12009843B2 ## CPC - H03M 7/30: Compression (speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N); Expansion; Suppression of unnecessary data, e.g. redundancy reduction - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/0495: Quantised networks; Sparse networks; Compressed networks - G06N 3/063: using electronic means - H03M 7/3082: {Vector coding (for television signals, see H04N19/94)} - H03M 7/6029: {Pipelining} - H03M 7/6064: {Selection of Compressor} - G06N 3/045: Combinations of networks - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed. The system implements LDC using a 2D-to-1D transformation of 2D uncompressed data blocks (2DU) within LDM to generate 1D uncompressed data blocks (1DU). The 1DU is then compressed to generate a 1D compressed superblock (CSB) in LDM. This LDM CSB may then be written to EDM with a reduced number of EDM bus cycles. The system implements LDD using decompression of CSB data retrieved from EDM to generate a 1D decompressed data block (1DD) in LDM. A 1D-to-2D transformation is then applied to the LDM 1DD to generate a 2D decompressed data block (2DD) in LDM. This 2DD may then be operated on by a matrix compute engine (MCE) using a variety of function operators. ## Claims ### Claim 1 A system comprising: a first memory; a second memory; and a matrix compression accelerator coupled to the first and second memories, wherein the matrix compression accelerator is configured to: receive 2D uncompressed data from the first memory, wherein the 2D uncompressed data includes a first set of data blocks; transform the 2D uncompressed data to 1D uncompressed data that includes a second set of data blocks that is a subset of the first set of data blocks of the 2D uncompressed data, wherein the second set of data blocks is not contiguous in the 2D uncompressed data and is contiguous in the 1D uncompressed data; compressing at least a subset of the 1D uncompressed data to generate a compressed superblock; and storing the compressed superblock in the second memory. ### Claim 2 (depends on 1) The system of claim 1, wherein the compressed superblock is stored in the second memory using a dispersed direct memory access data transfer. ### Claim 3 (depends on 1) The system of claim 1, wherein the compressed superblock is stored in the second memory using an integrated direct memory access data transfer. ### Claim 4 (depends on 1) The system of claim 1, wherein the matrix compression accelerator is configured to store a compression mode vector in the second memory, the compression mode vector comprises one data bit for each data block of the second set of data blocks in the 1D uncompressed data that indicates whether the respective data block is compressed in the compressed superblock. ### Claim 5 (depends on 1) The system of claim 1, wherein the matrix compression accelerator is configured to store a compression mode vector in the second memory, the compression mode vector comprises one data bit for each byte of the 1D uncompressed data that indicates whether a respective portion of the compressed superblock is compressed. ### Claim 6 (depends on 1) The system of claim 1, wherein the compressed superblock has a fixed bit width equivalent to an integer multiple of a data bus width of the first memory. ### Claim 7 (depends on 1) The system of claim 1, wherein the first memory has a data bus width of 128 bytes. ### Claim 8 (depends on 1) The system of claim 1, wherein the compressed superblock comprises data fields incorporating lossless data compression. ### Claim 9 A method comprising: receiving, from a first memory, a set of 2D uncompressed data that includes a first set of data blocks; transforming, by a matrix compression accelerator, the 2D uncompressed data to 1D uncompressed data that includes a second set of data blocks that is a subset of the first set of data blocks, wherein the second set of data blocks is not contiguous in the 2D uncompressed data and is contiguous in the 1D uncompressed data; compressing, by the matrix compression accelerator, a subset of the 1D uncompressed data to produce a compressed superblock comprising compressed data and uncompressed data; and storing, by the matrix compression accelerator, the compressed superblock in a second memory. ### Claim 10 (depends on 9) The method of claim 9, wherein the compressed superblock is stored in the second memory using a dispersed direct memory access data transfer. ### Claim 11 (depends on 9) The method of claim 9, wherein the compressed superblock is stored in the second memory using an integrated direct memory access data transfer. ### Claim 12 (depends on 9) The method of claim 9, further comprising storing a compression mode vector in the second memory, the compression mode vector comprises one data bit for each data block of the second set of data blocks in the 1D uncompressed data that indicates whether the respective data block is compressed in the compressed superblock. ### Claim 13 (depends on 9) The method of claim 9, further comprising storing a compression mode vector in the second memory, the compression mode vector comprises one data bit for each byte of the 1D uncompressed data that indicates whether a respective portion of the compressed superblock is compressed. ### Claim 14 (depends on 9) The method of claim 9, wherein the compressed superblock has a fixed bit width equivalent to an integer multiple of a data bus width of the first memory. ### Claim 15 (depends on 9) The method of claim 9, wherein the first memory has a data bus width of 128 bytes. ### Claim 16 (depends on 9) The method of claim 9, wherein the compressed superblock comprises data fields incorporating lossless data compression.