# US 12,009,842 B2 · Error correcting code circuitry compatible with multi-width interfaces

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- Number: US 12,009,842 B2
- Document ID: US12009842B2
- Status: Granted
- Kind: B2
- Application number: 16/723,910
- Filed: 2019-12-20
- Published: 2020-04-23
- Granted: 2024-06-11
- Earliest claimed: 2019-12-20
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Qiang Wang
- Web page: https://patentgrep.com/patent/US12009842B2

## CPC

- H03M 13/6356: {by repetition or insertion of dummy data, i.e. rate reduction}
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- G06F 13/1678: {using bus width}
- H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
- H03M 13/6516: {Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields}
- H03M 13/27: using interleaving techniques
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Systems and methods described herein may relate to providing a dynamically configurable error correction code (ECC) circuitry able to process data having one of a variety of widths. This multi-width ECC circuitry may generate error correction code bits (ECC bits) using, for example, an encoder or a decoder characterized by a fixed data width. Translation circuitry (e.g., a format converter) may translate data received from data utilization circuitry between a data width used by the data utilization circuitry and the fixed data width used by the encoder or the decoder.

## Claims

### Claim 1

An integrated circuit, comprising:
data utilization circuitry configurable to generate first data characterized by a first data width; and
configurable error correction code (ECC) circuitry communicatively coupled between the data utilization circuitry and a memory comprising a memory interface, wherein the configurable ECC circuitry comprises an encoder having a second data width, and wherein the configurable ECC circuitry is configurable to:
receive the first data from the data utilization circuitry;
adjust the first data characterized by the first data width into second data characterized by the second data width configurable to be processed by the encoder to generate ECC bits before being stored in the memory, wherein the encoder is configurable to generate the ECC bits based on a logarithmic relationship between the first data width and the second data width;
process, via an output format converter, the ECC bits to pad the ECC bits with one or more dummy ECC bits to match a width of the ECC bits padded by the one or more dummy ECC bits to a width of the memory interface; and
write the ECC bits padded by the one or more dummy ECC bits to the memory.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the encoder comprises a fixed data width as the second data width that does not change between two accesses of the memory.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the data utilization circuitry is configurable to generate the first data at a first time and third data comprising the second data width at a second time.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the first data comprises non-encoded data generated by the data utilization circuitry.

### Claim 5 (depends on 4)

The integrated circuit of claim 4, wherein the first data is transmitted with padding data to the configurable ECC circuitry, and wherein the first data and the padding data collectively are characterized by the second data width.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein the ECC bits are characterized by a third data width, and wherein the configurable ECC circuitry comprises:
a first format converter configurable to adjust the ECC bits from the third data width to a format compatible with the memory.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, wherein the third data width is represented by a relationship:
width=k+(log2(m)+1)
wherein k corresponds to a multiplier to use to increase the second data width to the first data width or a number of data widths, and wherein m corresponds to a number of bits equal to a minimum data width of the configurable ECC circuitry.

### Claim 8 (depends on 6)

The integrated circuit of claim 6, wherein the second data comprises the first data without comprising dummy bits.

### Claim 9 (depends on 6)

The integrated circuit of claim 6, wherein the first data is adjusted via adding data padding, wherein the data padding comprises one or more dummy bits, and wherein each dummy bit comprises no data of the first data.

### Claim 10 (depends on 1)

The integrated circuit of claim 1, wherein the one or more dummy ECC bits are configurable as logical low values inserted to one or more predetermined bit positions.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the one or more dummy ECC bits are configurable to be interleaved with the ECC bits at the one or more predetermined bit positions.

### Claim 12 (depends on 1)

The integrated circuit of claim 1, wherein the width of the memory interface corresponds to a number of bits able to be transmitted via a plurality of parallel couplings to the memory interface from a multi-width memory interface circuitry.

### Claim 13 (depends on 1)

The integrated circuit of claim 1, wherein the output format converter is configurable to generate the one or more dummy ECC bits based on a data width parameter and a format parameter received from a configuration register, wherein the data padding generator is configurable to adjust the first data into the second data based on the format parameter, and wherein the configuration register is configurable to be programmed with the data width parameter and the format parameter when receiving configuration data corresponding to programmable logic circuitry that generated the first data.

### Claim 14

A method, comprising:
receiving first input data characterized by a first data width;
adjusting the first input data into second data characterized by a second data width;
generating error correction code (ECC) bits characterized by a third data width using an encoder characterized by the second data width, wherein the ECC bits are generated based on a logarithmic relationship between the third data width and the second data width;
processing, via an output format converter configurable to couple to a memory via a memory interface characterized by a fourth data width, the ECC bits to pad the ECC bits with one or more dummy ECC bits to match the fourth data width; and
writing the ECC bits padded by the one or more dummy ECC bits to the memory via the memory interface.

### Claim 15 (depends on 14)

The method of claim 14, comprising:
receiving third input data characterized by a fifth data width different from the first data width and the second data width;
adjusting the third input data into fourth data characterized by the second data width; and
generating additional ECC bits using the encoder.

### Claim 16 (depends on 14)

The method of claim 14, comprising:
reading the ECC bits padded by the one or more dummy ECC bits from the memory;
decoding the ECC bits using a decoder characterized by a fifth data width to generate the first input data characterized by the first data width from the ECC bits; and
in response to decoding the ECC bits, transmitting the first input data from the decoder to data utilization circuitry.

### Claim 17

A device comprising:
a format converter communicatively coupled to a memory via a memory interface having a first data width; and
encoding circuitry comprising an input characterized by a second data width communicatively coupled to the format converter, wherein the encoding circuitry is configurable to receive input data having a third data width padded to the second data width and to generate first data having a fourth data width;
wherein the format converter is configurable to:
receive the first data characterized by the fourth data width from the encoding circuitry, wherein the first data comprises error correction code (ECC) bits generated by the encoding circuitry, wherein the first data is generated based on a logarithmic relationship between the fourth data width and the second data width;
generate second data at least in part by padding the first data with one or more dummy ECC bits, wherein the second data is characterized by the first data width; and
write the second data to the memory via the memory interface.

### Claim 18 (depends on 17)

The device of claim 17, wherein the fourth data width is equal to a first relationship:
width=k+(log2(m)+1)
wherein k corresponds to a multiplier to use to increase the third data width to the fourth data width or a number of data widths, and wherein m corresponds to a number of bits equal to a minimum data width of the encoding circuitry.

### Claim 19 (depends on 17)

The device of claim 17, wherein the format converter is configurable to adjust data from the memory to be input into decoding circuitry based at least in part on a data width parameter read from a configuration register.