Systems and methods of decoding error correction code of a memory device with dynamic bit error estimation

A system to decode error correction code of a memory device with dynamic bit error estimation, the system comprising:

• a controller to generate at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device;
• a first decoder integrated with the memory device, to decode the code word in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property;
• and
• a second decoder integrated with the memory device, to decode the code word in response to a determination that the metric does not satisfy the threshold associated with the syndromes, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding, the second decoder having a second execution property distinct from the first execution property,
• wherein the controller is further configured to generate at least one second metric corresponding to the syndromes associated with the code word, and
• the first decoder is further configured to decode the code word in response to the determination that the metric satisfies the threshold, and in response to a determination the second metric satisfies a second threshold.

A non-transitory computer readable medium including one or more instructions stored thereon and executable by a processor to:

• generate, by the processor, a first metric comprising a number of unsolved syndromes associated with a code word, the code word comprising an error correction code of a memory device;
• generate, by the processor, a second metric comprising a number of solvable syndromes associated with the code word;
• decode, by the processor, the code word by a first decoder integrated with the memory device, in response to a determination that the first metric is less than a first threshold number of unsolved syndromes the first decoder having a first execution property;
• and
• decode, by the processor, the code word by a second decoder integrated with the memory device, in response to a determination that the first metric is not less than the first threshold number of unsolved syndromes but the second metric is less than a second threshold number of solvable syndromes, the second decoder having a second execution property distinct from the first execution property.