Syndrome calculation for error detection and error correction

A memory system comprising:

• a non-volatile memory;
• and
• a memory controller including a controller circuit configured to control reading of data from the non-volatile memory and an error correction circuit, the error correction circuit including a syndrome calculation circuit and an error correction control circuit, wherein
• the controller circuit inputs data bits based on data read from the non-volatile memory,
• the syndrome calculation circuit generates syndrome bits in a first composite field by calculating a first matrix product of the input data bits and a first arithmetic matrix, and generates syndrome bits in a second composite field by calculating a second matrix product of the input data bits and a second arithmetic matrix, wherein
• the first arithmetic matrix is a matrix product of a first basis conversion matrix for converting a data string from a Galois field to the first composite field and a third arithmetic matrix, which is at least a part of a first parity check matrix,
• the second arithmetic matrix is a matrix product of a second basis conversion matrix for converting a data string from the Galois field to the second composite field and a fourth arithmetic matrix, which is at least a part of a second parity check matrix,
• the error correction control circuit performs error detection and error correction of the input data bits based on the syndrome bits, and
• the controller circuit outputs error-corrected data bits to a host.