# US 12,009,835 B2 · Command address fault detection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,835 B2 - Document ID: US12009835B2 - Status: Granted - Kind: B2 - Application number: 17/814,402 - Filed: 2022-07-22 - Published: 2024-01-25 - Granted: 2024-06-11 - Earliest claimed: 2022-07-22 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Aaron P. Boehm; Melissa I. Uribe - Web page: https://patentgrep.com/patent/US12009835B2 ## CPC - H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit - H03M 13/1174: {Parity-check or generator matrices built from sub-matrices representing known block codes such as, e.g. Hamming codes, e.g. generalized LDPC codes} - G11C 7/109: {Control signal input circuits} - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 29/022: {in I/O circuitry} - G11C 29/42: using error correcting codes [ECC] or parity check - H03M 13/098: {using single parity bit} - G11C 29/025: {in signal lines} - G11C 2029/0411: {Online error correction} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of bits associated with a command signal or an address signal. The CA bus may be configured for communicating command signals and address signals between the memory device and the host device. The memory device may generate one or more parity bits based on the plurality of bits. The one or more parity bits may be generated using a parity generation process that is common to the memory device and the host device. The memory device may transmit, to the host device, the one or more parity bits. ## Claims ### Claim 1 A memory device, comprising: one or more components configured to: receive, from a host device via a command address bus, a plurality of bits associated with a command signal or an address signal, wherein the command address bus is configured for communicating command signals and address signals between the memory device and the host device; generate one or more parity bits based on applying a parity generation process to the plurality of bits that are received via the command address bus, wherein the parity generation process is common to the memory device and the host device; and transmit, to the host device, the one or more parity bits. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the one or more components, to transmit the one or more parity bits, are configured to transmit the one or more parity bits via a dedicated parity pin. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the one or more components, to transmit the one or more parity bits, are configured to transmit the one or more parity bits via a unidirectional pin from the memory device to the host device. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the unidirectional pin is a data pin. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the one or more components, to receive the plurality of bits, are configured to receive a first set of bits associated with a first unit interval and a second set of bits associated with a second unit interval. ### Claim 6 (depends on 5) The memory device of claim 5, wherein the one or more components, to generate the one or more parity bits, are configured to generate the one or more parity bits based on the first set of bits and the second set of bits. ### Claim 7 (depends on 5) The memory device of claim 5, wherein the first set of bits associated with the first unit interval is received via a first command address bus and the second set of bits associated with the second unit interval is received via a second command address bus. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the one or more components, to transmit the one or more parity bits, are configured to transmit the one or more parity bits in accordance with an interval. ### Claim 9 (depends on 1) The memory device of claim 1, wherein the one or more components, to generate the one or more parity bits, are configured to generate the one or more parity bits using a parity generator, wherein the parity generator receives the plurality of bits from a command path that is located between the command address bus and the parity generator. ### Claim 10 A system, comprising: a host device configured to: generate a plurality of bits associated with a command signal or an address signal; transmit the plurality of bits to a memory device via a command address bus, wherein the command address bus is configured for communicating command signals and address signals between the memory device and the host device; generate a first set of parity bits based on applying a parity generation process to the plurality of bits that are transmitted via the command address bus; receive a second set of parity bits from the memory device; and compare the first set of parity bits and the second set of parity bits; and the memory device, wherein the memory device is configured to: receive, from the host device via the command address bus, the plurality of bits; generate the second set of parity bits based on applying the parity generation process to the plurality of bits that are received via the command address bus; and transmit, to the host device, the second set of parity bits. ### Claim 11 (depends on 10) The system of claim 10, wherein the host device is further configured to determine a validity of the plurality of bits based on comparing the first set of parity bits and the second set of parity bits. ### Claim 12 (depends on 11) The system of claim 11, wherein the host device, to determine the validity of the plurality of bits, is configured to: determine that the plurality of bits are valid based on the first set of parity bits being identical to the second set of parity bits; or determine that the plurality of bits are invalid based on the first set of parity bits being different than the second set of parity bits. ### Claim 13 (depends on 12) The system of claim 12, wherein the host device is further configured to initiate a safety procedure based on determining that the plurality of bits are invalid. ### Claim 14 (depends on 10) The system of claim 10, wherein the memory device, to transmit the second set of parity bits, is configured to transmit the second set of parity bits via a dedicated parity pin, and wherein the host device, to receive the second set of parity bits, is configured to receive the second set of parity bits via the dedicated parity pin. ### Claim 15 (depends on 10) The system of claim 10, wherein the memory device, to transmit the second set of parity bits, is configured to transmit the second set of parity bits via a unidirectional data pin, and wherein the host device, to receive the second set of parity bits, is configured to receive the second set of parity bits via the unidirectional data pin. ### Claim 16 (depends on 10) The system of claim 10, wherein the host device, to transmit the plurality of bits, is configured to transmit a first set of bits using a first unit interval and a second set of bits via a second unit interval, and wherein the memory device, to receive the plurality of bits, is configured to receive the first set of bits using the first unit interval and the second set of bits using the second unit interval. ### Claim 17 (depends on 16) The system of claim 16, wherein the memory device, to generate the first set of parity bits, is configured to generate the first set of parity bits based on the first set of bits and the second set of bits. ### Claim 18 (depends on 10) The system of claim 10, wherein the memory device, to generate the second set of parity bits, is configured to generate the second set of parity bits using a parity generator, wherein the parity generator receives the plurality of bits from a command path that is located between the command address bus and the parity generator. ### Claim 19 (depends on 10) The system of claim 10, wherein the memory device, to transmit the second set of parity bits, is configured to transmit the second set of parity bits in accordance with an interval. ### Claim 20 A method performed by a memory device, comprising: receiving, from a host device via a command address bus, a plurality of bits associated with a command signal or an address signal, wherein the command address bus is configured for communicating command signals and address signals between the memory device and the host device; generating one or more parity bits based on applying a parity generation process to the plurality of bits that are received via the command address bus; and transmitting, to the host device via a parity pin, the one or more parity bits. ### Claim 21 (depends on 20) The method of claim 20, wherein the parity pin is a unidirectional data pin. ### Claim 22 (depends on 20) The method of claim 20, wherein the parity generation process is common to the memory device and the host device. ### Claim 23 (depends on 20) The method of claim 20, wherein receiving the plurality of bits comprises receiving a first set of bits using a first unit interval and a second set of bits using a second unit interval. ### Claim 24 (depends on 23) The method of claim 23, wherein generating the one or more parity bits comprises generating the one or more parity bits based on the first set of bits and the second set of bits. ### Claim 25 (depends on 23) The method of claim 23, wherein the first set of bits associated with the first unit interval is received via a first command address bus and the second set of bits associated with the second unit interval is received via a second command address bus.