# US 12,009,833 B2 · Method for synchronising analogue data at the output of a plurality of digital/analogue converters

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- Number: US 12,009,833 B2
- Document ID: US12009833B2
- Status: Granted
- Kind: B2
- Application number: 17/636,820
- Filed: 2020-08-19
- Published: 2022-09-22
- Granted: 2024-06-11
- Earliest claimed: 2019-08-20
- Assignees: Teledyne E2V Semiconductors SAS
- Applicants: Teledyne e2v Semiconductors SAS
- Inventors: Quentin Béraud-Sudreau; Jérôme Ligozat; Rémi Laube; Marc Stackler
- Web page: https://patentgrep.com/patent/US12009833B2

## CPC

- H03M 1/1255: {Synchronisation of the sampling frequency or phase to the input frequency or phase}
- G11C 7/1036: {using data shift registers}
- H03K 19/1774: {for global signals, e.g. clock, reset}
- H03M 1/1215: {using time-division multiplexing}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the number counted for the core. Device for implementing such a method.

## Claims

### Claim 1

A method for synchronizing analog data (Data_ana1, Data_ana2, Data_ana1) at an output of a plurality of digital/analog converters (DAC, DAC1, DAC2, DACI), comprising at least one conversion core (C, C1, C2), on an active edge of a common reference clock (Clk), characterized in that the method comprises the following steps:
a) Supplying an external synchronization signal (SYNC_ext), emitted by a control unit (UC), to at least one converter of the plurality of converters, and supplying a clock signal of the common reference clock to the plurality of converters;
b) Generating, within each converter of the plurality of converters, an internal synchronization signal (SYNC_int, SYNC_int1, SYNC_int2, SYNC_int1) from the external synchronization signal, such that all the internal synchronization signals are aligned on an active edge of the common reference clock;
c) Generating, by means of at least one electronic circuit internal to each converter of the plurality of converters, a start signal (START1, START2, STARTI) which represents a start of sending of digital data (Data_num1, Data_num2, Data_num1) by the control unit, on each core of the plurality of converters, and counting a number of clock strokes between the generation of the start signal and the generation of the internal synchronization signal for each of the cores of the plurality of converters; and
d) Applying a delay Ri (R1, R2, RI) to each core i of the plurality of converters, the delay being equal to the difference between the highest number counted in step c) and the number counted in step c) for the core i, i being an integer between 1 and the number of cores of the plurality of converters.

### Claim 2 (depends on 1)

The method for synchronizing analog data according to claim 1, wherein the internal synchronization signals are generated in step b) by resampling the external synchronization signal.

### Claim 3 (depends on 1)

The method for synchronizing analog data according to claim 1, wherein the converters of the plurality of converters form a serial transmission chain for the external synchronization signal, and step a) also comprises:
initializing, in each converter of the plurality of converters, a synchronization circuit (CS, CS1, CS2, CSI) comprising at least one polarity parameter defining, as polarity of a reference clock edge, for detecting signals at an input of the synchronization circuit of the converters, the polarity of the reference clock active edge or the opposite polarity; and
Step b) also comprises:
detecting a synchronization signal (SYNC_ext, SYNC_int1, SYNC_int2) at the input of the synchronization circuits of each converter, on a reference clock edge, which has the polarity defined by a value of the polarity parameter of the synchronization circuit; and
aligning, on the following active edge, the detected signal in order to supply an internal synchronization signal (SYNC_int1, SYNC_int2, SYNC_int1) aligned on a reference clock active edge at an output of the synchronization circuit of the converter.

### Claim 4

A device for synchronizing analog data at an output of a plurality of digital/analog converters on an active edge of a common reference clock (Clk), the device comprising:
the plurality of digital/analog converters (DAC, DAC1, DAC2, DACI) comprising:
N conversion cores (C, C1, C2) and
N memories (M, M1, M2),
each converter comprising at least one digital input, at least one analog output, at least one of the N memories, at least one of the N conversion cores and a synchronization circuit (CS, CS1, CS2, CSI) connected to the digital input, the synchronization circuits of the converters being connected to one another in a cascade, the memories of the converters each being connected to a conversion core of the converter and the synchronization circuit of the converters being configured so as to generate an internal synchronization signal (SYNC_int, SYNC_int1, SYNC_int2, SYNC_int1) and so that the internal synchronization signals generated are aligned on an active edge of a common clock, and N being an integer greater than or equal to 1; and
a control unit (UC) configured so as to send a signal from the common reference clock (Clk), an external synchronization signal (SYNC_ext) and digital data (Data_num1, Data_num2, Data_num1) to each converter;
Characterized in that each converter also comprises a data decoding circuit (Dec1, Dec2, Dec), comprising a counter (Cpt, Cpt1, Cpt2), for each conversion core included in the converter, the data decoding circuits being placed at an output of the synchronization circuit and at an input of the memories and being configured so as to generate start signals (START1, START2, STARTI) which represent a start of the sending of the digital data on a conversion core, and each counter being configured so as to count a number of clock strokes between the generation of the start signal and the generation of the internal synchronization signal for the conversion core, and in that an ith memory is configured so as to apply a delay Ri (R1, R2, RI) to an ith conversion core, i being an integer between 1 and N.

### Claim 5 (depends on 4)

The device for synchronizing analog data according to claim 4, wherein the control unit comprises at least one programmable logic circuit configured to send the external synchronization signal.

### Claim 6 (depends on 5)

The device for synchronizing analog data according to claim 5, wherein the plurality of converters comprises N converters, each converter comprising a single conversion core from the N conversion cores.

### Claim 7 (depends on 4)

The device for synchronizing analog data according to claim 4, wherein the control unit comprises at least one programmable logic circuit configured to send the digital data.

### Claim 8 (depends on 6)

The device for synchronizing analog data according to claim 6, wherein the plurality of converters comprises N converters, each converter comprising a single conversion core from the N conversion cores.

### Claim 9 (depends on 8)

The device for synchronizing analog data according to claim 8, wherein the plurality of converters comprises N converters, each converter comprising a single conversion core from the N conversion cores.

### Claim 10 (depends on 5)

The device for synchronizing analog data according to claim 5, wherein the control unit comprises at least one programmable logic circuit configured to send the digital data.

### Claim 11 (depends on 7)

The device for synchronizing analog data according to claim 7, wherein the plurality of converters comprises N converters, each converter comprising a single conversion core from the N conversion cores.

### Claim 12 (depends on 7)

The device for synchronizing analog data according to claim 7, wherein the control unit is also configured to receive the number of clock strokes counted by the N counters, to determine the delays Ri and to supply, to the N memories, a delay value Ri to be applied to the ith conversion core.

### Claim 13 (depends on 7)

The device for synchronizing analog data according to claim 7, wherein the N memories are shift registers.

### Claim 14 (depends on 4)

The device for synchronizing analog data according to claim 4, wherein the control unit is also configured to receive the number of clock strokes counted by the N counters, to determine the delays Ri and to supply, to the N memories, a delay value Ri to be applied to the ith conversion core.

### Claim 15 (depends on 14)

The device for synchronizing analog data according to claim 14, wherein the N memories are shift registers.

### Claim 16 (depends on 4)

The device for synchronizing analog data according to claim 4, wherein the N memories are shift registers.

### Claim 17 (depends on 16)

The device for synchronizing analog data according to claim 16, wherein the plurality of converters comprises N converters, each converter comprising a single conversion core from the N conversion cores.

### Claim 18 (depends on 4)

The device for synchronizing analog data according to claim 4, wherein the plurality of converters comprises N converters, each converter comprising a single conversion core from the N conversion cores.