# US 12,009,827 B2 · Monitor circuitry for power management and transistor aging tracking > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,827 B2 - Document ID: US12009827B2 - Status: Granted - Kind: B2 - Application number: 17/698,844 - Filed: 2022-03-18 - Published: 2022-06-30 - Granted: 2024-06-11 - Earliest claimed: 2020-06-26 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Kuan-Yueh Shen; Nasser A. Kurd; John Fallin - Web page: https://patentgrep.com/patent/US12009827B2 ## CPC - H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop - H03L 7/0992: {comprising a counter or a frequency divider} - H01R 13/665: {with built-in electronic circuit (H01R13/70, H01R13/719 take precedence)} - H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input} - H03L 7/0893: {the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop} - H03L 7/095: using a lock detector (H03L7/087 takes precedence) - H03L 7/101: {using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop (H03L7/113, H03L7/187 take precedence)} - H03L 7/1072: {by changing characteristics of the charge pump, e.g. changing the gain} - H03L 7/1075: {by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence)} - H03L 7/189: comprising a D/A converter for generating a coarse tuning voltage - H01R 2201/06: for computer periphery - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS ## Abstract Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node. ## Claims ### Claim 1 An apparatus comprising: a first circuit on a die; and a delay locked loop coupled to the first circuit, the delay locked loop including a first circuit path on the die, the first circuit path including a phase frequency detector having a first input node to receive a first signal, and a circuit node to provide a voltage based on a comparison between the first signal at the first input node of the phase frequency detector and a second signal at a second input node of the phase frequency detector; a delay line included in the delay locked loop, the delay line including an input node to receive the first signal and an output node to provide the second signal having a frequency based on a frequency of the first signal, the delay line including a second circuit coupled to the circuit node, the second circuit including a replica of the first circuit; a second circuit path included in the delay locked loop and coupled between the delay line and the second input node of the phase frequency detector; and an analog-to-digital converter coupled to the circuit node. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first circuit includes a logic gate and the second circuit includes a replica of the logic gate. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the second circuit includes a transistor, the transistor having a non-gate terminal coupled to the circuit node. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first path includes a charge pump coupled to the phase frequency detector. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the first path includes a filter coupled to the charge pump. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the first path includes a transistor having a gate coupled to an output of the filter. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the first path includes a first additional transistor coupled between the transistor and a supply node, and a second additional transistor coupled between the supply node and the circuit node. ### Claim 8 (depends on 1) The apparatus of claim 1, further comprising a third circuit path included in the delay locked loop, the third circuit including a current mirror coupled to the circuit node. ### Claim 9 An apparatus comprising: a processor including a processing circuitry and a delay locked loop coupled to the processing circuitry, the processing circuitry including a logic circuit path, the logic circuit path including a first circuit coupled to the delay locked loop, the delay locked loop including: a first circuit path including a phase frequency detector having a first input node to receive a first signal, and a circuit node to provide a voltage based on a comparison between the first signal at the first input node of the phase frequency detector and a second signal at a second input node of the phase frequency detector; a delay line including an input node to receive the first signal and an output node to provide the second signal having a frequency based on a frequency of the first signal, the delay line including a second circuit coupled to the circuit node, the second circuit including a replica of the first circuit; and a second circuit path coupled between the delay line and the second input node of the phase frequency detector. ### Claim 10 (depends on 9) The apparatus of claim 9, further comprising an analog-to-digital converter coupled to the circuit node. ### Claim 11 (depends on 9) The apparatus of claim 9, further comprising a connector coupled to the processor, the connector conforming with one of Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), and Ethernet specifications.