# US 12,009,817 B2 · Flip-flop circuit, semiconductor integrated circuit device, and vehicle > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,817 B2 - Document ID: US12009817B2 - Status: Granted - Kind: B2 - Application number: 17/898,690 - Filed: 2022-08-30 - Published: 2023-03-02 - Granted: 2024-06-11 - Earliest claimed: 2021-08-31 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Kazuya Ioki; Ryuichi Nakajima; Kazutoshi Kobayashi; Jun Furuta - Web page: https://patentgrep.com/patent/US12009817B2 ## CPC - H03K 19/0948: using CMOS {or complementary insulated gate field-effect transistors} - H03K 3/0372: {of the primary-secondary type} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A flip-flop circuit includes master latch including a first inverter and a first tri-state inverter, wherein the first tri-state inverter includes a first NMOS transistor and a first PMOS transistor; a slave latch including a second inverter and a second tri-state inverter, wherein the second tri-state inverter includes a second PMOS transistor and a second NMOS transistor; and at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor. ## Claims ### Claim 1 A flip-flop circuit comprising: a master latch including a first inverter and a first tri-state inverter configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor configured such that an inverted clock signal, which is an inversion of the clock signal, is input to the first PMOS transistor; a slave latch including a second inverter and a second tri-state inverter configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, wherein the second tri-state inverter includes a second PMOS transistor configured such that the clock signal is input to a gate of the second PMOS transistor, and a second NMOS transistor configured such that the inverted clock signal is input to the second NMOS transistor; and at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor, wherein the first tri-state inverter further includes two NMOS transistors directly connected to each other and configured such that output of the first inverter is input to gates of the two NMOS transistors. ### Claim 2 (depends on 1) The flip-flop circuit of claim 1, further comprising a third PMOS transistor connected in parallel to a PMOS transistor included in the first inverter and configured such that the output terminal of the first tri-state inverter is connected to a gate of the third PMOS transistor. ### Claim 3 (depends on 1) The flip-flop circuit of claim 1, wherein the second tri-state inverter includes two NMOS transistors directly connected to each other and configured such that output of the second inverter is input to gates of the two NMOS transistors. ### Claim 4 (depends on 3) The flip-flop circuit of claim 3, further comprising a fourth PMOS transistor connected in parallel to a PMOS transistor included in the second inverter and configured such that the output terminal of the second tri-state inverter is connected to a gate of the fourth PMOS transistor. ### Claim 5 (depends on 1) A semiconductor integrated circuit device comprising the flip-flop circuit of claim 1. ### Claim 6 (depends on 5) A vehicle comprising the semiconductor integrated circuit device of claim 5. ### Claim 7 A flip-flop circuit comprising: a master latch including a first inverter and a first tri-state inverter configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor configured such that an inverted clock signal, which is an inversion of the clock signal, is input to the first PMOS transistor; and a slave latch including a second inverter and a second tri-state inverter configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, wherein the second tri-state inverter includes a second PMOS transistor configured such that the clock signal is input to a gate of the second PMOS transistor, and a second NMOS transistor configured such that the inverted clock signal is input to the second NMOS transistor, wherein the first tri-state inverter further includes two NMOS transistors directly connected to each other and configured such that output of the first inverter is input to gates of the two NMOS transistors.