# US 12,009,815 B2 · Electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,815 B2 - Document ID: US12009815B2 - Status: Granted - Kind: B2 - Application number: 17/732,337 - Filed: 2022-04-28 - Published: 2022-11-03 - Granted: 2024-06-11 - Earliest claimed: 2021-04-28 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Seung Ho Lee; Gyu Nam Kim - Web page: https://patentgrep.com/patent/US12009815B2 ## CPC - H03K 19/018521: {of complementary type, e.g. CMOS} - H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) ## Abstract An electronic device uses, as power, a first voltage and a second voltage lower than the first voltage. The electronic device includes: an internal circuit configured to be driven by the second voltage, and output an output signal having a level corresponding to the second voltage; and an interface circuit configured to receive the output signal, the first voltage, and the second voltage, shift the output signal to a level corresponding to the first voltage, and provide the shifted output signal to a pad. The interface circuit includes an ESD (electrostatic discharge) block connected to the pad. The interface circuit further includes a plurality of transistors, and all of the transistors of the interface circuit are driven at the second voltage and broken at the first voltage. ## Claims ### Claim 1 An electronic device using, as power, a first voltage and a second voltage lower than the first voltage, the electronic device comprising: an internal circuit configured to be driven by the second voltage, and output an output signal having a level corresponding to the second voltage; and an interface circuit configured to receive the output signal, the first voltage, and the second voltage, shift the output signal to a level corresponding to the first voltage, and provide the shifted output signal to a pad, wherein the interface circuit includes an ESD (electrostatic discharge) block connected to the pad, and wherein the interface circuit further includes a plurality of transistors and the plurality of transistors of the interface circuit are driven at the second voltage, wherein the ESD block includes an electrostatic detection circuit configured to set a first setup voltage based on a first control voltage and generate an electrostatic detection signal by detecting static electricity contained in the first setup voltage. ### Claim 2 (depends on 1) The electronic device according to claim 1, wherein the interface circuit includes: a pull-up driver including a first PMOS transistor, a second PMOS transistor, and a first impedance calibration circuit, the first PMOS transistor connected between a power terminal to which the first voltage is provided and a first connection node and controlled by a first control bias, the second PMOS transistor connected between the first connection node and the pad and being in a turned-on state, the first impedance calibration circuit connected to the first connection node to control an impedance of the first connection node based on the first control bias; and a pull-down driver including a first NMOS transistor and a second NMOS transistor, the first NMOS transistor connected between the pad and a second connection node and controlled by the second voltage, the second NMOS transistor connected between the second connection node and a ground voltage terminal, wherein the first PMOS transistor and the second PMOS transistor are driven by the second voltage, and a difference between the first control bias and the first voltage is substantially equal to or less than a maximum operating voltage of the first and the second PMOS transistors. ### Claim 3 (depends on 2) The electronic device according to claim 2, wherein the ESD block includes at least one of a first ESD block or a second EDS block, the first EDS block electrically coupled between the pad and the second PMOS transistor to protect electrostatic electricity, the second ESD block electrically coupled between the pad and the first NMOS transistor to protect the electrostatic electricity. ### Claim 4 (depends on 1) The electronic device, according to claim 1, wherein the ESD block further includes: a control voltage generation circuit configured to generate the first control voltage, a second control voltage, and a third control voltage by dividing a supply voltage; a driving control circuit configured to set a second setup voltage based on the second control voltage, and generate a driving control signal based on the electrostatic detection signal; and a discharge driving circuit configured to set a third setup voltage based on the third control voltage, and perform a discharge operation on electrostatic electricity contained in the third setup voltage based on the driving control signal. ### Claim 5 An electronic device using a first voltage and a second voltage higher than the first voltage as a power, the electronic device comprising: an internal circuit configured to be driven by the first voltage and output an output signal having a first voltage level; and an interface circuit including a level shifter configured to shift the first voltage level of the output signal to a second voltage level, a driving block configured to buffer the shifted output signal, and an ESD (electrostatic discharge) block configured to protect the internal circuit from ESD, wherein a plurality of transistors in the driving block are driven when the first voltage is applied as an operation voltage, and reliabilities of the plurality of transistors are damaged when the second voltage is applied as the operation voltage. ### Claim 6 (depends on 5) The electronic device according to claim 5, wherein the ESD block includes: a control voltage generation circuit configured to generate a first control voltage, a second control voltage, and a third control voltage by dividing a supply voltage; an electrostatic detection circuit configured to set a first setup voltage based on the first control voltage, and generate an electrostatic detection signal by detecting static electricity contained in the first setup voltage; a driving control circuit configured to set a second setup voltage based on the second control voltage, and generate a driving control signal based on the electrostatic detection signal; and a discharge driving circuit configured to set a third setup voltage based on the third control voltage, and perform a discharge operation on electrostatic electricity contained in the third setup voltage based on the driving control signal. ### Claim 7 (depends on 5) The electronic device according to claim 5, wherein the driving block includes: a pull-up driver connected between a power terminal and the ESD block, and a pull-down driver connected between the ESD block and a ground voltage terminal. ### Claim 8 (depends on 7) The electronic device according to claim 7, wherein the pull-up driver includes: a first PMOS transistor receiving the second voltage through the power terminal and a first control bias as a gate voltage; a second PMOS transistor connected between the first PMOS transistor and the ESD block, the second PMOS transistor being normally turned on; and a first impedance calibration circuit connected to a first connection node, which is a connection node between the first PMOS transistor and the second PMOS transistor, and configured to control an impedance of the first connection node based on the first control bias, wherein the first impedance calibration circuit includes at least one PMOS transistor. ### Claim 9 (depends on 8) The electronic device according to claim 8, wherein a difference between the first control bias and the second voltage is equal to or less than a maximum operating voltage of the first and second PMOS transistors. ### Claim 10 (depends on 8) The electronic device according to claim 8, wherein the pull-down driver includes: a first NMOS transistor connected to the ESD block, the first NMOS transistor being normally turned on; a second NMOS transistor connected between a second connection node and the ground voltage terminal, the second connection node being a connection node between the first NMOS transistor and the second NMOS transistor; and a second impedance calibration circuit connected to the second connection node, and configured to control an impedance of the second connection node based on a second control bias, wherein the second impedance calibration circuit includes at least one NMOS transistor. ### Claim 11 (depends on 7) The electronic device according to claim 7, wherein the ESD block further includes: a first ESD block electrically connected between a pad and the pull-up driver, and configured to control an impedance of the pull-up driver; and a second ESD block electrically connected between the pad and the pull down driver and configured to control an impedance of the pull-down driver.