# US 12,009,793 B2 · Dual-mode power amplifier for wireless communication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,793 B2 - Document ID: US12009793B2 - Status: Granted - Kind: B2 - Application number: 18/175,593 - Filed: 2023-02-28 - Published: 2023-06-29 - Granted: 2024-06-11 - Earliest claimed: 2021-06-30 - Assignees: Silicon Laboratories Inc. - Applicants: Silicon Laboratories Inc. - Inventors: Ruifeng Sun; Sherry Wu; Michael S. Johnson; Vitor Pereira - Web page: https://patentgrep.com/patent/US12009793B2 ## CPC - H03F 3/245: {with semiconductor devices only} - H03F 1/0233: {by using a signal derived from the output signal, e.g. bootstrapping the voltage supply} - H03F 1/223: {with MOSFET's} - H03F 3/193: with field-effect devices (H03F3/195 takes precedence) - H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)} - H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal - H04B 1/04: Circuits - H04L 27/12: Modulator circuits; Transmitter circuits - H03F 2200/105: A non-specified detector of the power of a signal being used in an amplifying circuit - H03F 2200/451: the amplifier being a radio frequency amplifier - H04B 2001/0408: {with power amplifiers} - H04L 27/2626: {Arrangements specific to the transmitter only} - H03F: AMPLIFIERS - H04B: TRANSMISSION - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs. ## Claims ### Claim 1 A dual-mode power amplifier comprising: a transistor stack comprising a first plurality of metal oxide semiconductor field effect transistors (MOSFETs) of a first polarity and a second plurality of MOSFETs of a second polarity; a first buffer pair to receive a variable envelope signal of a first modulation scheme and provide the variable envelope signal to a gate terminal of a first MOSFET of the first plurality of MOSFETs and a gate terminal of a first MOSFET of the second plurality of MOSFETs; and a second buffer pair to receive a constant envelope signal of a second modulation scheme and provide the constant envelope signal to the gate terminal of the first MOSFET of the first plurality of MOSFETs and the gate terminal of the first MOSFET of the second plurality of MOSFETs. ### Claim 2 (depends on 1) The dual-mode power amplifier of claim 1, further comprising: a first coupling capacitor coupled between a first buffer of the first buffer pair and the first MOSFET of the first plurality of MOSFETs; and a second coupling capacitor coupled between a second buffer of the first buffer pair and the first MOSFET of the second plurality of MOSFETs. ### Claim 3 (depends on 1) The dual-mode power amplifier of claim 1, wherein the transistor stack comprises: a second MOSFET of the first plurality of MOSFETs coupled to the first MOSFET of the first plurality of MOSFETs, wherein a first terminal of the second MOSFET of the first plurality of MOSFETs is coupled to an output node of the dual-mode power amplifier; and a second MOSFET of the second plurality of MOSFETs coupled to the first MOSFET of the second plurality of MOSFETs, wherein a first terminal of the second MOSFET of the second plurality of MOSFETs is coupled to the output node. ### Claim 4 (depends on 3) The dual-mode power amplifier of claim 3, further comprising a bias circuit to: provide a first bias voltage to the second MOSFET of the first plurality of MOSFETs when operation is according to the first modulation scheme, to minimize switching resistance of the second MOSFET of the first plurality of MOSFETs; and provide a second bias voltage to the second MOSFET of the second plurality of MOSFETs when the operation is according to the second modulation scheme, to bias the second MOSFET of the second plurality of MOSFETs at a minimal gate voltage to maintain device reliability. ### Claim 5 (depends on 4) The dual-mode power amplifier of claim 4, further comprising a controller to control the dual-mode power amplifier to operate in a linear mode to output the variable envelope signal and to operate in a switching mode to output the constant envelope signal. ### Claim 6 (depends on 5) The dual-mode power amplifier of claim 5, wherein the controller is to control the bias circuit to provide the first bias voltage to the second MOSFET of the first plurality of MOSFETs in the linear mode and provide the second bias voltage to the second MOSFET of the first plurality of MOSFETs in the switching mode, the first bias voltage different than the second bias voltage. ### Claim 7 An apparatus comprising: a digital core; a sensor circuit coupled to the digital core; and a transceiver coupled to the digital core, the transceiver comprising a dual-mode power amplifier, the dual-mode power amplifier comprising: a transistor stack comprising a first plurality of metal oxide semiconductor field effect transistors (MOSFETs) of a first polarity and a second plurality of MOSFETs of a second polarity; first input MOSFETs to receive a variable envelope signal of a first modulation scheme and provide the variable envelope signal to a second terminal of a first MOSFET of the first plurality of MOSFETs and a second terminal of a first MOSFET of the second plurality of MOSFETs; and second input MOSFETs to receive a constant envelope signal of a second modulation scheme and provide the constant envelope signal to the second terminal of the first MOSFET of the first plurality of MOSFETs and the second terminal of the first MOSFET of the second plurality of MOSFETs. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the transistor stack comprises partially shared driving MOSFETs coupled between a supply voltage node and a reference voltage node. ### Claim 9 (depends on 7) The apparatus of claim 7, wherein the transistor stack comprises: a second MOSFET of the first plurality of MOSFETs coupled to the first MOSFET of the first plurality of MOSFETs, wherein a first terminal of the second MOSFET of the first plurality of MOSFETs is coupled to an output node of the dual-mode power amplifier; and a second MOSFET of the second plurality of MOSFETs coupled to the first MOSFET of the second plurality of MOSFETs, wherein a first terminal of the second MOSFET of the second plurality of MOSFETs is coupled to the output node. ### Claim 10 (depends on 7) The apparatus of claim 7, further comprising: first coupling capacitors coupled to the first input MOSFETs; and second coupling capacitors coupled to the second input MOSFETs. ### Claim 11 (depends on 7) The apparatus of claim 7, further comprising a controller to control the dual-mode power amplifier to operate in a linear mode to output the variable envelope signal and to operate in a switching mode to output the constant envelope signal. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the dual-mode power amplifier comprises a plurality of slices, each of the plurality of slices comprising the transistor stack, wherein the controller is to controllably select a number of the plurality of slices to be enabled. ### Claim 13 (depends on 11) The apparatus of claim 11, wherein the controller is to control a bias circuit to provide a first bias voltage to a gate terminal of a second MOSFET of the first plurality of MOSFETs in the linear mode and provide a second bias voltage to the gate terminal of the second MOSFET of the first plurality of MOSFETs in the switching mode, the first bias voltage different than the second bias voltage. ### Claim 14 (depends on 7) The apparatus of claim 7, wherein the apparatus comprises an Internet of Things (IoT) device comprising at least one of a sensor, an actuator, or a controller. ### Claim 15 A dual-mode power amplifier comprising: a first plurality of metal oxide semiconductor field effect transistors (MOSFETs) of a first polarity and a second plurality of MOSFETs of a second polarity; first input MOSFETs to receive a variable envelope signal of an orthogonal frequency division multiplexing (OFDM) modulation scheme and provide the variable envelope signal to a second terminal of a first MOSFET of the first plurality of MOSFETs and a second terminal of a first MOSFET of the second plurality of MOSFETs; second input MOSFETs to receive a constant envelope signal of a frequency shift keying (FSK) modulation scheme and provide the constant envelope signal to the second terminal of the first MOSFET of the first plurality of MOSFETs and the second terminal of the first MOSFET of the second plurality of MOSFETs; a second MOSFET of the first plurality of MOSFETs coupled to the first MOSFET of the first plurality of MOSFETs, wherein a first terminal of the second MOSFET of the first plurality of MOSFETs is to output an amplified variable envelope signal and an amplified constant envelope signal; a second MOSFET of the second plurality of MOSFETs coupled to the first MOSFET of the second plurality of MOSFETs, wherein a first terminal of the second MOSFET of the second plurality of MOSFETs is to output the amplified variable envelope signal and the amplified constant envelope signal; and a controller to control the dual-mode power amplifier to operate in a linear mode to output the amplified variable envelope signal and to operate in a switching mode to output the amplified constant envelope signal. ### Claim 16 (depends on 15) The dual-mode power amplifier of claim 15, wherein the dual-mode power amplifier comprises a plurality of slices, wherein the controller is to controllably select a number of the plurality of slices to be enabled. ### Claim 17 (depends on 15) The dual-mode power amplifier of claim 15, wherein the controller is to control a bias circuit to provide a first bias voltage to a gate terminal of the second MOSFET of the first plurality of MOSFETs in the linear mode and provide a second bias voltage to the gate terminal of the second MOSFET of the first plurality of MOSFETs in the switching mode, the first bias voltage different than the second bias voltage. ### Claim 18 (depends on 15) The dual-mode power amplifier of claim 15, further comprising: a third MOSFET of the first plurality of MOSFETs coupled to one of the first input MOSFETs and one of the second input MOSFETs; and a third MOSFET of the second plurality of MOSFETs coupled to a different one of the first input MOSFETs and a different one of the second input MOSFETs.