# US 12,009,437 B2 · Method for manufacturing a semiconductor structure having group III-V device on group IV substrate and contacts with liner stacks

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- Number: US 12,009,437 B2
- Document ID: US12009437B2
- Status: Granted
- Kind: B2
- Application number: 17/977,503
- Filed: 2022-10-31
- Published: 2023-02-16
- Granted: 2024-06-11
- Earliest claimed: 2020-01-10
- Assignees: Newport Fab, LLC
- Applicants: Newport Fab, LLC
- Inventors: Edward Preisler; Zhirong Tang
- Web page: https://patentgrep.com/patent/US12009437B2

## CPC

- H10F 30/223: the potential barrier being a PIN barrier
- H10F 77/933: {for devices having potential barriers}
- H10F 30/222: the potential barrier being a PN heterojunction
- H10F 71/127: {The active layers comprising only Group III-V materials, e.g. GaAs or InP}
- H10F 71/1272: {comprising at least three elements, e.g. GaAlAs or InGaAsP}
- H10F 71/139: {using temporary substrates}
- H10F 77/124: comprising only Group III-V materials, e.g. GaAs
- H10F 77/147: {Shapes of bodies}
- H10F 77/206: {for devices having potential barriers}
- H10F 77/407: {indirectly associated with the devices}
- H10W 90/00: Package configurations
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over the patterned group III-V device. A liner stack having at least one metal liner is situated in each contact hole. Filler metals are situated over each liner stack and fill the contact holes. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.

## Claims

### Claim 1

A method comprising:
providing a group IV substrate and a group III-V chiplet, said group IV substrate including a group IV device;
bonding said group III-V chiplet to said group IV substrate;
patterning said group III-V chiplet to produce a patterned group III-V device;
forming a blanket dielectric layer over said patterned group III-V device;
forming a first contact hole and a second contact hole in said blanket dielectric layer, said first contact hole over said patterned group III-V device, said second contact hole over said group IV device;
forming a liner stack in said first contact hole and said second contact hole substantially concurrently and directly contacting both a group III-V portion of said patterned group III-V device and said group IV device; and
depositing a filler metal in said first contact hole and said second contact hole over said liner stack.

### Claim 2 (depends on 1)

The method of claim 1, wherein said liner stack directly contacts another group III-V portion of said patterned group III-V device.

### Claim 3 (depends on 1)

The method of claim 1, wherein said forming said liner stack comprises forming at least one metal liner is selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and nickel (Ni).

### Claim 4 (depends on 1)

The method of claim 1, wherein said forming said liner stack comprises:
forming a titanium (Ti) metal liner; and
forming a titanium nitride (TiN) metal liner over said Ti metal liner.

### Claim 5 (depends on 4)

The method of claim 4, wherein said filler metal comprises tungsten (W).

### Claim 6 (depends on 1)

The method of claim 1, wherein said patterned group III-V device is a patterned group III-V photodiode comprising an N type cathode and a P type anode.

### Claim 7 (depends on 6)

The method of claim 6, wherein said N type cathode comprises indium phosphide (InP), and said P type anode comprises indium gallium arsenide (InGaAs).

### Claim 8 (depends on 1)

The method of claim 1, further comprising planarizing said blanket dielectric layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein said patterned group III-V device is optically connected to another group IV device in said group IV substrate.

### Claim 10 (depends on 1)

The method of claim 1, wherein said patterned III-V device is electrically connected to said group IV device in said group IV substrate.

### Claim 11

A method comprising:
bonding a group III-V chiplet to a group IV substrate, said group IV substrate including a group IV device;
patterning said group III-V chiplet to produce a patterned group III-V device;
forming a dielectric layer over said patterned group III-V device;
forming a first contact hole and a second contact hole in said dielectric layer, said first contact hole over said patterned group III-V device, said second contact hole over said group IV device;
forming a liner stack in said first contact hole and said second contact hole substantially concurrently and directly contacting both a group III-V portion of said patterned group III-V device and said group IV device; and
depositing a filler metal in said first contact hole and said second contact hole.

### Claim 12 (depends on 11)

The method of claim 11, wherein said liner stack directly contacts another group III-V portion of said patterned group III-V device.

### Claim 13 (depends on 11)

The method of claim 11, wherein said forming said liner stack comprises forming at least one metal liner is selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and nickel (Ni).

### Claim 14 (depends on 11)

The method of claim 11, wherein said forming said liner stack comprises:
forming a titanium (Ti) metal liner; and
forming a titanium nitride (TiN) metal liner over said Ti metal liner.

### Claim 15 (depends on 11)

The method of claim 11, wherein said filler metal comprises tungsten (W).

### Claim 16 (depends on 11)

The method of claim 11, wherein said patterned group III-V device is a patterned group III-V photodiode comprising an N type cathode and a P type anode.

### Claim 17 (depends on 16)

The method of claim 16, wherein said N type cathode comprises indium phosphide (InP), and said P type anode comprises indium gallium arsenide (InGaAs).

### Claim 18 (depends on 11)

The method of claim 11, further comprising planarizing said dielectric layer.

### Claim 19 (depends on 11)

The method of claim 11, wherein said patterned group III-V device is optically connected to another group IV device in said group IV substrate.

### Claim 20 (depends on 11)

The method of claim 11, wherein said patterned III-V device is electrically connected to said group IV device in said group IV substrate.