# US 12,009,435 B2 · Integrated nanosheet field effect transistors and floating gate memory cells

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- Number: US 12,009,435 B2
- Document ID: US12009435B2
- Status: Granted
- Kind: B2
- Application number: 17/473,151
- Filed: 2021-09-13
- Published: 2023-03-16
- Granted: 2024-06-11
- Earliest claimed: 2021-09-13
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruilong Xie; Julien Frougier; Veeraraghavan S. Basker; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US12009435B2

## CPC

- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10B 43/00: EEPROM devices comprising charge-trapping gate insulators
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10P 14/3452: {Microstructure}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device including a nanosheet field effect transistor (FET) comprising a thin gate oxide layer and a floating gate memory cell comprising a tunneling oxide, a floating gate, and a blocking oxide layer over a fin FET device. The device fabricated by forming a nanosheet stack and fin structures, forming tunneling oxide and floating gate layers over the nanosheet stack and fin structures, forming dummy gate structures over the nanosheet stack and fin structures, removing the dummy gate structures, forming a blocking oxide layer over the floating gate, and forming replacement metal gates.

## Claims

### Claim 1

A semiconductor device comprising: a nanosheet field effect transistor (FET) comprising a gate oxide layer; and
a floating gate memory cell comprising a tunneling oxide, a floating gate, a dielectric isolation layer, and a blocking oxide layer over a fin FET device.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the tunneling oxide and floating gate layers are disposed beneath a gate contact and the blocking oxide is disposed beneath and beside the gate contact.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the FET and floating gate memory cell are disposed at a common device level.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the floating gate memory comprises a vertical blocking oxide layer disposed adjacent to a control gate.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the FET further comprises a dielectric isolation layer.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the floating gate memory cell further comprises a plurality of fins.

### Claim 7

A method of fabricating a semiconductor device, the method comprising:
forming a nanosheet stack and fin structures;
forming tunneling oxide and floating gate layers over the nanosheet stack and fin structures;
forming dummy gate structures over the nanosheet stack and fin structures;
exposing the floating gate;
forming a blocking oxide layer over the floating gate; and
forming replacement metal gates.

### Claim 8 (depends on 7)

The method according to claim 7, further comprising forming an oxide layer adjacent to the blocking oxide layer and the nanosheet stack.

### Claim 9 (depends on 7)

The method according to claim 7, further comprising forming a dielectric isolation layer beneath a field effect transistor.

### Claim 10 (depends on 7)

The method according to claim 7, further comprising forming a dielectric isolation layer beneath a floating gate memory cell.

### Claim 11 (depends on 7)

The method according to claim 7, wherein the nanosheet stack and fin structures are formed at a common device level.

### Claim 12 (depends on 7)

The method according to claim 7, wherein the replacement metal gate is formed adjacent to vertical blocking oxide layers.

### Claim 13 (depends on 8)

The method according to claim 8, wherein the tunneling oxide and the floating gate layers are disposed beneath a gate contact and the blocking oxide is disposed beneath and beside the gate contact.

### Claim 14

A method of fabricating a semiconductor device comprising a field effect transistor (FET) and a floating gate memory cell, the method comprising:
forming a nanosheet stack for the FET;
forming at least one fin structure for the floating gate memory;
forming tunneling oxide and floating gate layers over the fin structure;
forming dummy gate structures over the nanosheet stack and fin structures;
exposing the floating gate layer of the floating gate memory;
forming a blocking oxide layer over the floating gate; and
forming a replacement metal gate adjacent to the blocking oxide layer.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the tunneling oxide and the floating gate layers are disposed beneath a gate contact and the blocking oxide is disposed beneath and beside the gate contact.

### Claim 16 (depends on 14)

The method according to claim 14, further comprising forming an oxide layer adjacent to the blocking oxide layer and the nanosheet stack.

### Claim 17 (depends on 14)

The method according to claim 14, further comprising forming a dielectric isolation layer beneath a field effect transistor.

### Claim 18 (depends on 14)

The method according to claim 14, further comprising forming a dielectric isolation layer beneath a floating gate memory cell.

### Claim 19 (depends on 14)

The method according to claim 14, wherein the nano sheet stack and fin structures are formed at a common device level.