# US 12,009,434 B2 · Semiconductor device including transistors and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,434 B2 - Document ID: US12009434B2 - Status: Granted - Kind: B2 - Application number: 18/098,769 - Filed: 2023-01-19 - Published: 2023-05-18 - Granted: 2024-06-11 - Earliest claimed: 2008-10-24 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Hidekazu Miyairi; Takeshi Osada; Shunpei Yamazaki - Web page: https://patentgrep.com/patent/US12009434B2 ## CPC - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions} - H10D 30/6729: {characterised by the electrodes} - H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 30/6733: {Multi-gate TFTs} - H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs} - H10D 62/80: characterised by the materials - H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates} - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10D 86/021: {of multiple TFTs} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs} - H10D 86/60: wherein the TFTs are in active matrices - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)} - H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass - H10P 95/90: Thermal treatments, e.g. annealing or sintering - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced. ## Claims ### Claim 1 A semiconductor device comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor and a first wiring, wherein the first wiring has a function of transmitting a signal which is output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor, wherein a first conductive layer has a function of a gate of the first transistor, wherein a second conductive layer has a function of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, wherein a third conductive layer has a function of a gate of the second transistor, wherein the first conductive layer is electrically connected to the third conductive layer through the second conductive layer, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring, wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring, wherein the gate of the third transistor is electrically connected to a gate of the fifth transistor, and wherein the second transistor comprises a channel formation region over and overlapping with the third conductive layer. ### Claim 2 A semiconductor device comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor and a first wiring, wherein the first wiring has a function of transmitting a signal which is output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor, wherein a first conductive layer has a function of a gate of the first transistor, wherein a second conductive layer has a function of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, wherein a third conductive layer has a function of a gate of the second transistor, wherein the first conductive layer is electrically connected to the third conductive layer through the second conductive layer, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring, wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring, wherein the gate of the third transistor is electrically connected to a gate of the fifth transistor, wherein the second transistor comprises a channel formation region over and overlapping with the third conductive layer, and wherein the first conductive layer is electrically connected to the third conductive layer without a semiconductor layer therebetween.