# US 12,009,433 B2 · Multi-dielectric gate stack for crystalline thin film transistors

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- Number: US 12,009,433 B2
- Document ID: US12009433B2
- Status: Granted
- Kind: B2
- Application number: 16/001,837
- Filed: 2018-06-06
- Published: 2019-12-12
- Granted: 2024-06-11
- Earliest claimed: 2018-06-06
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Van H. Le; Inanc Meric; Gilbert Dewey; Sean Ma; Abhishek A. Sharma; Miriam Reshotko; Shriram Shivaraman; Kent Millard; Matthew V. Metz; Wilhelm Melitz; Benjamin Chu-Kung; Jack Kavalieros
- Web page: https://patentgrep.com/patent/US12009433B2

## CPC

- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10D 30/0312: {characterised by the gate electrodes}
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.

## Claims

### Claim 1

A thin film transistor, comprising:
a substrate;
a gate electrode over the substrate;
a gate dielectric stack over the gate electrode, wherein the gate dielectric stack comprises a plurality of layers, the plurality of layers comprising a first layer of 1, 2, 11, 12, 14, 18, 20, and 22, a layer of Al2O3 on the first layer of HfO2, and a second layer of HfO2 on the layer of Al2O3, wherein a first one of the plurality of layers has a first thickness, and a second one of the plurality of layers has a second thickness different than the first thickness;
a semiconductor layer over the gate dielectric stack, wherein the semiconductor layer comprises a crystalline semiconductor layer in direct contact with the second layer of HfO2 of the gate dielectric stack; and
a source electrode and a drain electrode, both the source electrode and the drain electrode directly on and in contact with the crystalline semiconductor layer, wherein the gate electrode extends laterally at least as wide as the semiconductor layer and at least as wide as the gate dielectric stack.

### Claim 2 (depends on 1)

The thin film transistor of claim 1, wherein an uppermost layer of the gate dielectric stack is amorphous.

### Claim 3 (depends on 1)

The thin film transistor of claim 1, wherein a thickness of each of the plurality of layers of the gate dielectric stack is less than 10 nm.

### Claim 4 (depends on 3)

The thin film transistor of claim 3, wherein a thickness of each of the plurality of layers of the gate dielectric stack is less than 5 nm.

### Claim 5

A method of forming a thin film transistor, comprising:
forming a gate electrode over a substrate;
forming a gate dielectric stack over the gate electrode, wherein the gate dielectric stack comprises a first layer of HfO2 in direct contact with the gate electrode, a layer of Al2O3 on the first layer of HfO2, and a second layer of HfO2 on the layer of Al2O3, and wherein a first layer of the gate dielectric stack has a first thickness, and a second layer of the dielectric stack has a second thickness different than the first thickness;
forming a semiconductor layer over the gate dielectric stack, wherein the semiconductor layer comprises a crystalline semiconductor layer in direct contact with the second layer of HfO2 of the gate dielectric stack; and
forming a source electrode and a drain electrode directly on the crystalline semiconductor layer, wherein the gate electrode extends laterally at least as wide as the semiconductor layer and at least as wide as the gate dielectric stack.

### Claim 6 (depends on 5)

The method of claim 5, wherein the gate dielectric stack is formed with an atomic layer deposition (ALD) process.

### Claim 7 (depends on 5)

The method of claim 5, wherein each of the dielectric layers has a thickness less than 10 nm.

### Claim 8

A computing device, comprising:
an integrated circuit die, wherein the integrated circuit die comprises a thin film transistor, wherein the thin film transistor comprises:
a substrate;
a gate electrode over the substrate;
an amorphous gate dielectric over the gate electrode, wherein the amorphous gate dielectric comprises a plurality of layers, the plurality of layers comprising a first layer of HfO2 in direct contact with the gate electrode, a layer of Al2O3 on the first layer of HfO2, and a second layer of HfO2 on the layer of Al2O3, and wherein a first layer of the amorphous gate dielectric has a first thickness, and a second layer of the amorphous gate dielectric has a second thickness different than the first thickness;
a crystalline semiconductor layer over and in direct contact with the second layer of HfO2 of the amorphous gate dielectric; and
a source electrode and a drain electrode, both the source electrode and the drain electrode directly on and in contact with the crystalline semiconductor layer, wherein the gate electrode extends laterally at least as wide as the semiconductor layer and at least as wide as the amorphous gate dielectric.