# US 12,009,429 B2 · Semiconductor device and method

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- Number: US 12,009,429 B2
- Document ID: US12009429B2
- Status: Granted
- Kind: B2
- Application number: 17/872,825
- Filed: 2022-07-25
- Published: 2022-11-10
- Granted: 2024-06-11
- Earliest claimed: 2020-06-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Lien Huang; Guan-Ren Wang; Ching-Feng Fu
- Web page: https://patentgrep.com/patent/US12009429B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 64/668: {the layer being a silicide, e.g. TiSi2}
- H10D 84/0137: {the gate conductors being silicided}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/047: {by introducing additional elements therein}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

## Claims

### Claim 1

A device comprising:
a gate structure over a channel region of a substrate;
a source/drain region adjacent the channel region;
a first inter-layer dielectric over the source/drain region;
a silicide between the first inter-layer dielectric and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region;
a first void exposing a surface of the silicide and the bottom surface of the source/drain region; and
a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first inter-layer dielectric, the second portion of the first source/drain contact extending through the first inter-layer dielectric and contacting the silicide.

### Claim 2 (depends on 1)

The device of claim 1 further comprising:
a gate spacer separating the source/drain region from the gate structure, a sidewall of the gate spacer contacting the silicide and the first source/drain contact; and
a contact etch stop layer extending along the sidewall of the gate spacer, the contact etch stop layer contacting the first source/drain contact.

### Claim 3 (depends on 1)

The device of claim 1 further comprising:
a gate spacer separating the source/drain region from the gate structure;
a contact etch stop layer extending along a sidewall of the gate spacer; and
a second void between the contact etch stop layer and the source/drain region, the second void exposing surfaces of the gate spacer, the silicide, and the first source/drain contact.

### Claim 4 (depends on 1)

The device of claim 1 further comprising:
a gate spacer separating the source/drain region from the gate structure; and
a contact etch stop layer extending along a sidewall of the gate spacer and the top surface of the source/drain region, the contact etch stop layer contacting the silicide and the first source/drain contact.

### Claim 5 (depends on 1)

The device of claim 1 further comprising:
a gate spacer separating the source/drain region from the gate structure;
a contact etch stop layer extending along a sidewall of the gate spacer and the top surface of the source/drain region; and
a second void between the first inter-layer dielectric and the source/drain region, the second void exposing surfaces of the contact etch stop layer, the silicide, and the first source/drain contact.

### Claim 6 (depends on 1)

The device of claim 1 further comprising:
a second inter-layer dielectric on the first inter-layer dielectric;
a second source/drain contact extending through the second inter-layer dielectric, the second source/drain contact contacting the first source/drain contact; and
a gate contact extending through the second inter-layer dielectric, the gate contact contacting the gate structure,
wherein top surfaces of the first inter-layer dielectric, the first source/drain contact, and the gate structure are coplanar, and
wherein top surfaces of the second inter-layer dielectric, the second source/drain contact, and the gate contact are coplanar.

### Claim 7 (depends on 1)

The device of claim 1 further comprising:
a second inter-layer dielectric on the first inter-layer dielectric, the first source/drain contact extending through the second inter-layer dielectric; and
a gate contact extending through the second inter-layer dielectric, the gate contact contacting the gate structure,
wherein top surfaces of the second inter-layer dielectric, the first source/drain contact, and the gate contact are coplanar.

### Claim 8 (depends on 1)

The device of claim 1, wherein a lower portion of the first source/drain contact is wider than an upper portion of the first source/drain contact.

### Claim 9

A device comprising:
a gate structure on a substrate;
a gate spacer adjacent the gate structure;
a source/drain region adjacent the gate spacer;
a silicide on the source/drain region, the silicide contacting a sidewall of the gate spacer;
a source/drain contact on the silicide, the source/drain contact contacting the sidewall of the gate spacer;
an inter-layer dielectric on a lower portion of the source/drain contact, the inter-layer dielectric surrounding an upper portion of the source/drain contact; and
a void exposing a surface of the inter-layer dielectric, a bottom surface of the source/drain region, and a surface of the silicide.

### Claim 10 (depends on 9)

The device of claim 9 further comprising:
a contact etch stop layer contacting a top surface of the source/drain contact, the sidewall of the gate spacer, and a sidewall of the inter-layer dielectric.

### Claim 11 (depends on 9)

The device of claim 9, wherein the silicide has a first portion and a second portion, the first portion disposed between the source/drain contact and a top surface of the source/drain region, the second portion disposed between the inter-layer dielectric and the bottom surface of the source/drain region.

### Claim 12 (depends on 9)

The device of claim 9, wherein the lower portion of the source/drain contact is wider than the upper portion of the source/drain contact.

### Claim 13 (depends on 9)

The device of claim 9, wherein the void exposes the sidewall of the gate spacer.

### Claim 14

A device comprising:
a semiconductor fin;
a source/drain region in the semiconductor fin, the source/drain region having facets which extend laterally outward beyond sidewalls of the semiconductor fin;
a dielectric layer on the source/drain region;
an inter-layer dielectric on the dielectric layer, the dielectric layer comprising a different dielectric material than the inter-layer dielectric;
a source/drain contact having a main portion extending through the inter-layer dielectric and the dielectric layer and having an undercut portion beneath the inter-layer dielectric, the source/drain contact coupled to the source/drain region, the dielectric layer separated from a sidewall of the source/drain contact by an air gap; and
a silicide between the source/drain contact and the source/drain region, the silicide extending along the facets of the source/drain region.

### Claim 15 (depends on 14)

The device of claim 14, wherein the silicide extends along upper facets of the source/drain region.

### Claim 16 (depends on 14)

The device of claim 14, wherein the silicide extends along lower facets of the source/drain region.

### Claim 17 (depends on 14)

The device of claim 14, wherein the undercut portion of the source/drain contact is wider than the main portion of the source/drain contact.

### Claim 18 (depends on 14)

The device of claim 14 further comprising:
a gate structure on the semiconductor fin; and
a gate spacer between the gate structure and the source/drain region, the gate spacer contacting a sidewall of the source/drain contact.

### Claim 19 (depends on 14)

The device of claim 14 further comprising:
a gate structure on the semiconductor fin; and
a gate spacer between the gate structure and the source/drain region, the gate spacer separated from a sidewall of the source/drain contact by an air gap.

### Claim 20 (depends on 14)

The device of claim 14 further comprising:
a gate structure on the semiconductor fin; and
a gate spacer between the gate structure and the source/drain region, the dielectric layer extending along a sidewall of the gate spacer.