# US 12,009,428 B2 · Semiconductor device and method

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- Number: US 12,009,428 B2
- Document ID: US12009428B2
- Status: Granted
- Kind: B2
- Application number: 17/812,874
- Filed: 2022-07-15
- Published: 2022-11-03
- Granted: 2024-06-11
- Earliest claimed: 2020-02-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Chuan Yang; Kuo-Hsiu Hsu; Feng-Ming Chang; Kian-Long Lim; Lien Jung Hung
- Web page: https://patentgrep.com/patent/US12009428B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/834: {comprising FinFETs}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.

## Claims

### Claim 1

A method comprising:
forming an anti-punch-through (APT) region in a top portion of a substrate;
depositing a multi-layer stack on the APT region, the multi-layer stack comprising alternating first semiconductor layers and second semiconductor layers;
etching the multi-layer stack to form a first recess exposing the APT region;
forming an epitaxial material on the APT region in the first recess;
etching the multi-layer stack and the epitaxial material to form a first nanostructure and a first semiconductor fin, respectively;
forming a shallow trench isolation region on the APT region adjacent the first nanostructure and the first semiconductor fin; and
forming gate stacks on the shallow trench isolation region, the first nanostructure, and the first semiconductor fin.

### Claim 2 (depends on 1)

The method of claim 1, further comprising planarizing the epitaxial material and the multi-layer stack.

### Claim 3 (depends on 2)

The method of claim 2, wherein planarizing the epitaxial material and the multi-layer stack removes a first semiconductor layer of the first semiconductor layers and exposes a second semiconductor layer of the second semiconductor layers.

### Claim 4 (depends on 1)

The method of claim 1, wherein etching the multi-layer stack and the epitaxial material to form the first nanostructure and the first semiconductor fin comprises:
forming a patterned mask layer on the multi-layer stack and the epitaxial material; and
removing the patterned mask layer and a first layer of the second semiconductor layers to expose a second layer of the first semiconductor layers.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming source/drain regions adjacent the gate stacks, wherein the source/drain regions extend at least partially into the APT region.

### Claim 6 (depends on 1)

The method of claim 1, wherein etching the multi-layer stack and the epitaxial material to form the first nanostructure and the first semiconductor fin comprises forming a patterned mask layer on the multi-layer stack and the epitaxial material, wherein a ratio of a first width of a first portion of the patterned mask layer on the multi-layer stack to a second width of a second portion of the patterned mask layer on the epitaxial material is from 3 to 8.

### Claim 7 (depends on 1)

The method of claim 1, further comprising removing the second semiconductor layers, wherein a topmost surface of a topmost first semiconductor layer is level with a topmost surface of the epitaxial material, and wherein a bottommost surface of a bottommost first semiconductor layer is level with a bottommost surface of the epitaxial material.

### Claim 8

A method comprising:
forming a multi-layer semiconductor stack on a semiconductor substrate, the multi-layer semiconductor stack comprising alternating first semiconductor layers and second semiconductor layers;
etching the multi-layer semiconductor stack to form a first opening exposing the semiconductor substrate;
forming an epitaxial material filling the first opening;
removing a topmost first semiconductor layer of the first semiconductor layers;
etching the multi-layer semiconductor stack and the epitaxial material to form a first nanostructure and a first fin, respectively;
removing a topmost second semiconductor layer of the second semiconductor layers;
forming gate stacks on the first nanostructure and the first fin; and
forming source/drain regions in the first nanostructure and the first fin adjacent the gate stacks.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming an anti-punch-through region in a top portion of the semiconductor substrate.

### Claim 10 (depends on 8)

The method of claim 8, further comprising forming a first patterned mask on the multi-layer semiconductor stack and the epitaxial material, wherein etching the multi-layer semiconductor stack and the epitaxial material to form the first nanostructure and the first fin comprises patterning the multi-layer semiconductor stack and the epitaxial material through the first patterned mask, and wherein removing the topmost second semiconductor layer of the second semiconductor layers further comprises removing the first patterned mask.

### Claim 11 (depends on 8)

The method of claim 8, wherein the first nanostructure is formed in an NMOS region, and wherein the first fin is formed in a PMOS region.

### Claim 12 (depends on 8)

The method of claim 8, further comprising removing the second semiconductor layers to form first recesses, wherein the gate stacks are formed in the first recesses.

### Claim 13 (depends on 8)

The method of claim 8, wherein forming the source/drain regions comprises:
forming first recesses extending through the multi-layer semiconductor stack and the epitaxial material into the semiconductor substrate; and
epitaxially growing the source/drain regions such that top surfaces of the source/drain regions are above top surfaces of the multi-layer semiconductor stack and the epitaxial material.

### Claim 14 (depends on 8)

The method of claim 8, wherein the first semiconductor layers and the epitaxial material comprise a first material, and wherein the second semiconductor layers comprise a second material different from the first material.

### Claim 15

A method comprising:
forming on a semiconductor substrate a multi-layer stack containing N layers, where N is an integer greater than two;
etching the multi-layer stack to form a first recess in a first region exposing the semiconductor substrate;
forming a first epitaxial material in the first recess;
planarizing the first epitaxial material and the multi-layer stack with a first planarizing process, wherein the first planarizing process removes a topmost layer of the N layers of the multi-layer stack, while leaving N−1 layers of the multi-layer stack intact;
patterning the N−1 layers of the multi-layer stack and the first epitaxial material to form a first nanostructure in a second region and a first fin in the first region; and
planarizing the first nanostructure and the first fin with a second planarizing process, wherein the second planarizing process removes a topmost layer of the N−1 layers of the multi-layer stack, while leaving N−2 layers of the multi-layer stack intact.

### Claim 16 (depends on 15)

The method of claim 15, wherein etching the multi-layer stack to form the first recess exposes an anti-punch-through region of the semiconductor substrate.

### Claim 17 (depends on 15)

The method of claim 15, wherein planarizing the first nanostructure and the first fin with the second planarizing process further comprises removing a patterned mask from on the first nanostructure and the first fin.

### Claim 18 (depends on 15)

The method of claim 15, wherein planarizing the first epitaxial material and the multi-layer stack with the first planarizing process removes a portion of the first epitaxial material extending on the multi-layer stack.

### Claim 19 (depends on 15)

The method of claim 15, wherein the first region is a PMOS region, and wherein the second region is an NMOS region.

### Claim 20 (depends on 15)

The method of claim 15, wherein the first epitaxial material and the first topmost layer of the multi-layer stack comprise a first material, and wherein the second topmost layer of the multi-layer stack comprises a second material different from the first material.