# US 12,009,427 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 12,009,427 B2
- Document ID: US12009427B2
- Status: Granted
- Kind: B2
- Application number: 17/978,027
- Filed: 2022-10-31
- Published: 2023-02-16
- Granted: 2024-06-11
- Earliest claimed: 2015-08-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kun-Mu Li; Tsz-Mei Kwok; Ming-Hua Yu; Chan-Lon Yang
- Web page: https://patentgrep.com/patent/US12009427B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/68: Organic materials, e.g. photoresists
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 32/20: Diffusion for doping of insulating layers
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

## Claims

### Claim 1

A semiconductor device, comprising:
a fin structure extending in a first direction disposed over a substrate, the fin structure including a well layer, an oxide layer disposed over the well layer, and a channel layer disposed over the oxide layer;
a gate structure extending in a second direction over the channel layer;
stressor layers disposed in the fin structure on opposing sides of the gate structure, wherein the stressor layers include a first stressor layer disposed over the well layer, a second stressor layer disposed over the first stressor layer, and a third stressor layer disposed over the second stressor layer, and
the first, second, and third stressor layers have different compositions; and
a dielectric layer disposed between the first stressor layer, the second stressor layer, the oxide layer, and the well layer,
wherein the dielectric layer and the oxide layer have different compositions.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the oxide layer includes SiGe oxide or Ge oxide.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the dielectric layer is in a range of 1 nm to 10 nm.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the stressor layers include at least one of SiC, SiP, SiGe, and Ge.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising side wall insulating layers disposed over side walls of the gate structure.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the dielectric layer is in contact with the side wall insulating layers.

### Claim 8

A semiconductor device, comprising:
a fin structure extending in a first direction disposed over a substrate, the fin structure including a well layer, an oxide layer disposed over the well layer, and a channel layer disposed over the oxide layer;
a gate structure extending in a second direction crossing over the fin structure; and
source/drain regions disposed in the fin structure on opposing sides of the gate structure, wherein the source/drain regions comprise:
a first epitaxial layer;
a second epitaxial layer disposed over the first epitaxial layer;
a third epitaxial layer disposed over the second epitaxial layer; and
a fourth epitaxial layer disposed over the third epitaxial layer,
wherein immediately adjacent epitaxial layers have different compositions; and
a dielectric layer comprising a first portion and a second portion,
wherein the first portion is disposed in contact with the oxide layer, the well layer, the first epitaxial layer, and the second epitaxial layer, and the second portion is disposed in contact with the fourth epitaxial layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the oxide layer includes SiGe oxide or Ge oxide.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein a height of the first epitaxial layer is substantially equal to or larger than a height of the oxide layer.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the source/drain regions include at least one of SiC, SiP, SiGe, and Ge.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, further comprising side wall insulating layers disposed over the gate structure.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the dielectric layer is further disposed over the side wall insulating layers.

### Claim 15

A semiconductor device, comprising:
a fin structure extending in a first direction disposed over a substrate, the fin structure including a well layer, an oxide layer disposed over the well layer, and a channel layer disposed over the oxide layer;
a gate dielectric layer disposed over the channel layer;
a gate electrode layer disposed over the gate dielectric layer,
wherein the gate dielectric layer and the gate electrode layer extend in a second direction crossing the first direction; and
source/drain regions disposed in the fin structure on opposing sides of the channel layer,
wherein the source/drain regions comprise:
a first epitaxial layer;
a second epitaxial layer disposed over the first epitaxial layer;
a third epitaxial layer disposed over the second epitaxial layer;
a fourth epitaxial layer disposed over the third epitaxial layer,
wherein immediately adjacent epitaxial layers have different compositions, and
wherein an upper surface of the third epitaxial layer is below a level of a lower surface of the gate electrode layer, and an upper surface of the fourth epitaxial layer is above a level of an upper surface the channel layer;
a dielectric layer disposed between the oxide layer, the well layer, the first epitaxial layer, and the second epitaxial layer,
a level of an upper surface of the dielectric layer is below a level of a lower surface of the channel layer, and
the oxide layer and the dielectric layer have different compositions.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the oxide layer includes SiGe oxide or Ge oxide.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein a height of the first epitaxial layer is substantially equal to or larger than a height of the oxide layer.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the source/drain regions include at least one of SiC, SiP, SiGe, and Ge.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, further comprising side wall insulating layers disposed over the gate structure, wherein the dielectric layer is further disposed over the side wall insulating layers.