# US 12,009,426 B2 · Structure and method for FinFET device with asymmetric contact

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- Number: US 12,009,426 B2
- Document ID: US12009426B2
- Status: Granted
- Kind: B2
- Application number: 17/827,457
- Filed: 2022-05-27
- Published: 2022-09-15
- Granted: 2024-06-11
- Earliest claimed: 2017-04-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon Jhy Liaw
- Web page: https://patentgrep.com/patent/US12009426B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/834: {comprising FinFETs}
- H10D 89/10: Integrated device layouts
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- Y02E 10/50: Photovoltaic [PV] energy
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

## Abstract

The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first fin active region protruding from a semiconductor substrate;
a first gate stack disposed over the first fin active region;
a first gate spacer disposed on a sidewall of the first gate stack;
a first source/drain feature formed on the first fin active region;
a first contact feature landing on the first source/drain feature; and
a dielectric feature interposed between the first gate spacer and the first contact feature, being in direct contact with both the first gate spacer and the first contact feature, wherein the first dielectric feature is overlying the first gate spacer and has a loop structure enclosing the first contact feature.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein a first sidewall of the first dielectric feature is aligned with a first sidewall of the first contact feature.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, further comprising
a second gate stack disposed over the first fin active region;
a second gate spacer disposed on a sidewall of the second gate stack; and
the dielectric feature extending between the second gate spacer and the first contact feature, being in direct contact with both the second gate spacer and the first contact feature.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein a second sidewall of the first dielectric feature is aligned with a second sidewall of the first contact feature.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein
the first contact feature includes a top portion and a bottom portion;
the bottom portion of the first contact feature spans first width between the first sidewall and the second sidewall of the dielectric feature; and
the top portion of the first contact feature spans a second width greater than the first width.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the top portion of the first contact feature contacts a top surface of the dielectric feature.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, further comprising a gate hard mask overlying the first gate stack, wherein the dielectric feature covers the first gate spacer and continuously extends to the gate hard mask.

### Claim 8 (depends on 6)

The semiconductor structure of claim 6, further comprising
a second source/drain feature on the fin active region; and
a second contact feature landing on the second source/drain feature, wherein
the first and second contact features are distanced away with opposing sidewalls and are aligned with parallel sidewalls,
the first and second contact features are enclosed by the dielectric feature in a top view, and
the dielectric feature contacts the parallel sidewalls and are free from the opposing sidewalls.

### Claim 9

A semiconductor structure, comprising:
an active region on a semiconductor substrate;
a gate stack disposed on the active region;
a gate dielectric cap overlying the gate stack;
a gate spacer of a first dielectric material disposed on sidewalls of the gate stack;
a contact feature landing on the active region; and
a dielectric layer of a second dielectric material disposed on a sidewall of the contact feature, wherein the dielectric layer is enclosing the contact feature in a top view.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the second dielectric material is different from the first dielectric material in composition.

### Claim 11 (depends on 9)

The semiconductor structure of claim 9, wherein the dielectric layer overlaps the gate spacer and spans between the gate dielectric cap and the contact feature.

### Claim 12 (depends on 9)

The semiconductor structure of claim 9, wherein the dielectric layer directly contacts the gate spacer and the contact feature.

### Claim 13

A semiconductor structure, comprising:
an active region on a semiconductor substrate;
a gate stack disposed on the active region;
a gate dielectric cap overlying the gate stack;
a gate spacer of a first dielectric material disposed on sidewalls of the gate stack;
a contact feature landing on the active region; and
a dielectric layer of a second dielectric material disposed between the gate spacer and contact feature, wherein the dielectric layer has a loop structure enclosing the contact feature in a top view.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein the dielectric layer is in direct contact with a sidewall of the gate spacer.

### Claim 15 (depends on 13)

The semiconductor structure of claim 13, wherein
the second dielectric material is different from the first dielectric material in composition, the first dielectric material includes silicon oxide, and
the second dielectric material includes a metal oxide dielectric material.

### Claim 16 (depends on 13)

The semiconductor structure of claim 13, wherein
the dielectric layer overlaps the gate spacer and spans between the gate dielectric cap and the contact feature, and
the dielectric layer directly contacts the contact feature.

### Claim 17 (depends on 13)

The semiconductor structure of claim 13, wherein the gate dielectric cap includes a third dielectric material different from the first and second dielectric materials in composition.

### Claim 18 (depends on 13)

The semiconductor structure of claim 13, further comprising
a second gate stack disposed partially on a first end of the active region and partially on a STI feature; and
a third gate stack disposed partially on a second end of the active region and partially on the STI feature.

### Claim 19 (depends on 13)

The semiconductor structure of claim 13, wherein the contact feature has an elongated shape with an L/W ratio defined as its length over its width, and wherein the L/W ratio is greater than 2.

### Claim 20 (depends on 13)

The semiconductor structure of claim 13, wherein the dielectric feature is recessed from the contact feature such that a top surface of the dielectric feature is below a top surface of the contact feature.