# US 12,009,424 B2 · Semiconductor device, and method for manufacturing the same

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- Number: US 12,009,424 B2
- Document ID: US12009424B2
- Status: Granted
- Kind: B2
- Application number: 17/541,845
- Filed: 2021-12-03
- Published: 2023-06-08
- Granted: 2024-06-11
- Earliest claimed: 2021-12-03
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Jhen-Yu Tsai
- Web page: https://patentgrep.com/patent/US12009424B2

## CPC

- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 64/01: Manufacture or treatment
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a first surface and a second surface protruding from the first surface of the substrate; a gate oxide layer disposed on the second surface of the substrate; and a first spacer disposed on the first surface of the substrate, and contacting the substrate and the gate oxide layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a first surface and a second surface protruding from the first surface of the substrate;
a gate oxide layer disposed on the second surface of the substrate;
a first spacer disposed on the first surface of the substrate, and contacting the substrate and the gate oxide layer;
a second spacer contacting the first spacer; and
a lightly doped region partially exposed from the first surface of the substrate and contacting the first spacer and the second spacer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the gate oxide layer is spaced apart from the first surface of the substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first surface of the substrate and the second surface of the substrate are substantially parallel.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a lateral surface of the gate oxide layer is substantially coplanar with a third surface of the substrate extending between the first surface of the substrate and the second surface of the substrate.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a gate conductive layer disposed on the gate oxide layer, wherein the first spacer further contacts the gate conductive layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a capping layer disposed on the gate conductive layer, wherein the first spacer extends between the capping layer and the first surface of the substrate.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second spacer is disposed on the first surface of the substrate.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the first spacer is disposed between the gate oxide layer and the second spacer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the lightly doped region is partially exposed from the second surface of the substrate.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising:
a heavily doped region disposed in the lightly doped region and partially exposed from the first surface of the substrate.

### Claim 11

A method of manufacturing a semiconductor device, comprising:
providing a substrate having a first surface and a second surface protruding from the first surface of the substrate;
forming a gate oxide layer on the second surface of the substrate;
forming a first spacer on the first surface of the substrate, and contacting the substrate and the gate oxide layer;
forming a second spacer contacting the first spacer; and
forming a lightly doped region partially exposed from the first surface of the substrate and contacting the first spacer and the second spacer.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
forming a gate conductive layer on the gate oxide layer, wherein the first spacer further contacts the gate conductive layer.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
forming a capping layer on the gate conductive layer, wherein the first spacer extends between the capping layer and the first surface of the substrate.

### Claim 14 (depends on 11)

The method of claim 11, wherein the second spacer is on the first surface of the substrate.

### Claim 15 (depends on 11)

The method of claim 11, wherein the first spacer is between the gate oxide layer and the second spacer.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
forming a heavily doped region in the lightly doped region and partially exposed from the first surface of the substrate.