# US 12,009,422 B2 · Self aligned top contact for vertical transistor

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- Number: US 12,009,422 B2
- Document ID: US12009422B2
- Status: Granted
- Kind: B2
- Application number: 17/453,874
- Filed: 2021-11-08
- Published: 2023-05-11
- Granted: 2024-06-11
- Earliest claimed: 2021-11-08
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: ChoongHyun Lee; Christopher J. Waskiewicz; Chanro Park; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US12009422B2

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure including a bottom source drain region arranged on a substrate; a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region; a metal gate disposed around the semiconductor channel region; a top source drain region above the semiconductor channel region; and a top contact partially embedded into the top source drain region.

## Claims

### Claim 1

A semiconductor structure comprising:
a bottom source drain region arranged on a substrate;
a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
a metal gate disposed around the semiconductor channel region;
a top source drain region above the semiconductor channel region; and
a top contact partially embedded into the top source drain region
a dielectric spacer separating the metal gate from the top source drain region, wherein a width of the dielectric spacer is substantially equal to a width of the top source drain region.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1,
wherein a width of the top source drain region is substantially equal to a combined width of the metal gate and the gate dielectric.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, further comprising:
a bottom spacer separating the bottom source drain region from the metal gate.

### Claim 4 (depends on 1)

The semiconductor structure according to claim 1, wherein a width of a lower portion of the top contact is smaller than a width of an upper portion of the top contact.

### Claim 5 (depends on 1)

The semiconductor structure according to claim 1, wherein a lower portion of the top contact is surrounded by the top source drain region and directly contacts a top surface of the semiconductor channel region.

### Claim 6 (depends on 1)

The semiconductor structure according to claim 1, wherein a bottom surface of an upper portion of the top contact covers a top surface of the top source drain region.

### Claim 7 (depends on 1)

The semiconductor structure according to claim 1, wherein a bottom surface of the top source drain region is below a top surface of the semiconductor channel region.

### Claim 8

A semiconductor structure comprising:
a bottom source drain region arranged on a substrate;
a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
a metal gate disposed around the semiconductor channel region;
a top source drain region above the semiconductor channel region;
a top contact partially embedded into the top source drain region, wherein sidewalls of the top contact are flush or substantially flush with sidewalls of the channel region; and
a gate liner separating the metal gate and the top source drain from an interlevel dielectric layer, wherein an uppermost surface of the gate liner is substantially flush with an uppermost surface of the top source drain region.

### Claim 9 (depends on 8)

The semiconductor structure according to claim 8, further comprising:
a dielectric spacer separating the metal gate from the top source drain region.

### Claim 10 (depends on 8)

The semiconductor structure according to claim 8, further comprising:
a bottom spacer separating the bottom source drain region from the metal gate.

### Claim 11 (depends on 8)

The semiconductor structure according to claim 8, wherein a width of a lower portion of the top contact is smaller than a width of an upper portion of the top contact.

### Claim 12 (depends on 8)

The semiconductor structure according to claim 8, wherein a lower portion of the top contact is surrounded by the top source drain region and directly contacts a top surface of the semiconductor channel region.

### Claim 13 (depends on 8)

The semiconductor structure according to claim 8, wherein a bottom surface of an upper portion of the top contact covers a top surface of the top source drain region.

### Claim 14 (depends on 8)

The semiconductor structure according to claim 8, wherein a bottom surface of the top source drain region is below a top surface of the semiconductor channel region.

### Claim 15

A method comprising:
forming a bottom source drain region arranged on a substrate;
forming a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
forming a metal gate disposed around the semiconductor channel region;
forming a dielectric spacer on the metal gate;
forming a top source drain region above the semiconductor channel region, wherein the dielectric spacer separates the metal gate from the top source drain region; and
forming a top contact partially embedded into the top source drain region.

### Claim 16 (depends on 1)

The semiconductor structure according to claim 1,
wherein a width of the top source drain region is substantially equal to a width of the metal gate plus a lateral width of the gate dielectric.

### Claim 17 (depends on 15)

The method according to claim 15, further comprising:
forming a bottom spacer separating the bottom source drain region from the metal gate.

### Claim 18 (depends on 15)

The method according to claim 15, wherein a width of a lower portion of the top contact is smaller than a width of an upper portion of the top contact.

### Claim 19 (depends on 15)

The method according to claim 15, wherein a lower portion of the top contact is surrounded by the top source drain region and directly contacts a top surface of the semiconductor channel region.

### Claim 20 (depends on 15)

The method according to claim 15, wherein a bottom surface of an upper portion of the top contact covers a top surface of the top source drain region.