# US 12,009,420 B2 · Semiconductor device, and method for manufacturing the same

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- Number: US 12,009,420 B2
- Document ID: US12009420B2
- Status: Granted
- Kind: B2
- Application number: 18/466,875
- Filed: 2023-09-14
- Published: 2024-01-04
- Granted: 2024-06-11
- Earliest claimed: 2008-03-26
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Yuki Nakano
- Web page: https://patentgrep.com/patent/US12009420B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 12/031: {of IGBTs}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/8325: {Silicon carbide}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10P 30/22: using masks
- H10D 62/154: {Dispositions}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor layer having a first face with a trench formed thereon and a second face opposite to the first face, a gate electrode, and a gate insulating layer. The semiconductor layer includes a first n-type semiconductor layer, a second n-type semiconductor layer, a p-type semiconductor layer, and an n-type semiconductor region. The trench is formed to penetrate through the p-type semiconductor layer and to reach the second n-type semiconductor layer. The p-type semiconductor layer includes an extended portion extending to a position closer to the second face of the semiconductor layer than the trench is. Such structure allows suppressing dielectric breakdown in the gate insulating layer.

## Claims

### Claim 1

A SiC semiconductor device comprising:
a layer of semiconductor made of silicon carbide having a first face provided with at least one trench and a second face opposite to the first face;
a gate electrode provided in the trench; and
an insulating layer provided in the trench so as to insulate the layer of semiconductor and the gate electrode from each other,
wherein the layer of semiconductor includes an n-type SiC semiconductor substrate with a high-concentration impurity, an n-type SiC semiconductor layer with a low-concentration impurity provided on the n-type SiC semiconductor substrate, a p-type SiC semiconductor layer provided on the n-type SiC semiconductor layer,
wherein the trench is formed so as to penetrate through the p-type SiC semiconductor layer and to reach the n-type SiC semiconductor layer,
wherein the p-type SiC semiconductor layer includes a close portion closer to the second face of the semiconductor layer than the trench is,
the p-type SiC semiconductor layer includes a channel region that is formed along the trench and held in contact with the n-type SiC semiconductor layer,
impurity concentration of the channel region is lower than impurity concentration of the close portion, and
the n-type SiC semiconductor layer and the close portion of the p-type SiC semiconductor layer define a bottom boundary at a lower level than the trench, with a field concentration taking place at the bottom boundary when a reverse bias is applied, thereby causing a breakdown of the insulating layer to be avoided.

### Claim 2 (depends on 1)

The SiC semiconductor device according to claim 1, wherein the impurity concentration of the close portion is 1×1017 cm−3 to 1×1020 cm−3 and the impurity concentration of the cannel region is 1×1016 cm−3 to 1×1019 cm−3.

### Claim 3 (depends on 1)

The SiC semiconductor device according to claim 1, wherein the n-type SiC semiconductor layer is an epitaxial grown layer.

### Claim 4 (depends on 1)

The SiC semiconductor device according to claim 1, wherein the n-type SiC semiconductor layer is in direct contact with a bottom of the trench.

### Claim 5 (depends on 1)

The SiC semiconductor device according to claim 1, further comprising an additional p-type SiC semiconductor layer formed below the bottom of the trench,
Wherein the additional p-type SiC semiconductor layer does not exist at any corner of the trench below the channel region.

### Claim 6 (depends on 1)

The SiC semiconductor device according to claim 1, further comprising a high-concentration semiconductor region of the p-type, the high-concentration semiconductor region including a part embedded in the p-type SiC semiconductor layer and spaced apart from the n-type SiC semiconductor layer,
wherein the bottom boundary that is located under the high-concentration semiconductor region in a depthwise direction of the trench and extends along a widthwise direction perpendicular to the depthwise direction, and
the bottom boundary is greater in size in the widthwise direction than the high-concentration semiconductor region.

### Claim 7 (depends on 1)

The SiC semiconductor device according to claim 1, wherein the layer of semiconductor comprises a wide band gap semiconductor.

### Claim 8 (depends on 1)

The SiC semiconductor device according to claim 1, wherein the at least one trench comprises a first trench and a second trench that are adjacent to each other, and the gate electrode comprises a first gate electrode provided in the first trench and a second gate electrode provided in the second trench.

### Claim 9 (depends on 8)

The SiC semiconductor device according to claim 8, further comprising a contact region between the first trench and the second trench.

### Claim 10 (depends on 9)

The SiC semiconductor device according to claim 9, further comprising a source region formed at a surface of the layer of the semiconductor.

### Claim 11 (depends on 10)

The SiC semiconductor device according to claim 10, wherein the source region is formed between the contact region and one of the first trench or the second trench.

### Claim 12 (depends on 11)

The SiC semiconductor device according to claim 11, further comprising a first insulating film and a second insulating film formed over the first gate electrode and the second gate electrode, respectively.

### Claim 13 (depends on 12)

The SiC semiconductor device according to claim 12, further comprising a source electrode formed over the first insulating film, the second insulating film and the first face of the layer of semiconductor.

### Claim 14 (depends on 13)

The SiC semiconductor device according to claim 13, wherein a surface of the source electrode includes an unevenness formed due to a thickness of each of the first insulating film and the second insulating film.

### Claim 15 (depends on 14)

The SiC semiconductor device according to claim 14, wherein a distance from the first trench to the contact region is same as a distance from the second trench to the contact region.

### Claim 16 (depends on 15)

The SiC semiconductor device according to claim 15, wherein a width of the contact region is smaller than a width of the close portion.

### Claim 17 (depends on 16)

The SiC semiconductor device according to claim 16, wherein a thickness of the close portion is greater than a thickness of the contact region.

### Claim 18 (depends on 17)

The SiC semiconductor device according to claim 17, wherein the layer of semiconductor further comprises a first semiconductor region and a second semiconductor region of the p-type, the first semiconductor region being formed around a bottom portion of the first trench, the second semiconductor region being formed along a bottom portion of the second trench.

### Claim 19 (depends on 18)

The SiC semiconductor device according to claim 18, wherein each of the first semiconductor region and the second semiconductor region includes a curved outline portion.

### Claim 20 (depends on 19)

The SiC semiconductor device according to claim 19, wherein the first trench and the second trench are symmetrical with respect to a center line of the close portion.