# US 12,009,419 B2 · Superjunction semiconductor device and method of manufacturing same

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- Number: US 12,009,419 B2
- Document ID: US12009419B2
- Status: Granted
- Kind: B2
- Application number: 17/569,284
- Filed: 2022-01-05
- Published: 2022-08-25
- Granted: 2024-06-11
- Earliest claimed: 2021-02-25
- Assignees: DB HiTek Co., Ltd.
- Applicants: DB HiTek Co., Ltd.
- Inventors: Yong Sin Han; Myeong Bum Pyun
- Web page: https://patentgrep.com/patent/US12009419B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 12/032: {of vertical IGBTs}
- H10D 12/441: {Vertical IGBTs}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/665: {having edge termination structures}
- H10D 62/054: {by high energy implantations in bulk semiconductor bodies, e.g. forming pillars}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 64/111: {Field plates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Disclosed are a superjunction semiconductor device and a method of manufacturing the same. More particularly, the present disclosure relates to a superjunction semiconductor device and a method of manufacturing the same, in which the device includes a field oxide layer having an uppermost end or surface that is higher than that of a gate oxide layer, between a gate electrode and a second pillar region in a cell region. This enables a reduction in gate-drain parasitic capacitance, thereby increasing switching speed and reducing switching loss.

## Claims

### Claim 1

A method of manufacturing a superjunction semiconductor device, the method comprising:
forming a second conductivity type epitaxial layer on a substrate;
forming a plurality of first conductivity type pillars in the epitaxial layer;
forming a first insulating layer on the epitaxial layer, and then forming a field oxide layer in a ring region and a gate insulating layer in a cell region by etching the first insulating layer using a first mask pattern;
forming a second insulating layer on the epitaxial layer after forming the field oxide layer and the gate insulating layer;
forming a gate layer on the field oxide layer, the gate insulating layer, and the second insulating layer; and
forming a gate oxide layer and a gate electrode by sequentially etching the gate layer and the second insulating layer using a second mask pattern,
wherein the gate insulating layer has at least one inclined surface extending obliquely upward.

### Claim 2

A method of manufacturing a superjunction semiconductor device, the method comprising:
forming a second conductivity type epitaxial layer on a substrate;
forming a plurality of first conductivity type pillars in the epitaxial layer;
forming a first insulating layer on the epitaxial layer, and then forming a field oxide layer in a ring region and a gate insulating layer in a cell region by etching the first insulating layer using a first mask pattern;
forming a second insulating layer on the epitaxial layer after forming the field oxide layer and the gate insulating layer;
forming a gate layer on the field oxide layer, the gate insulating layer, and the second insulating layer; and
forming a gate oxide layer and a gate electrode by sequentially etching the gate layer and the second insulating layer using a second mask pattern, wherein:
the gate insulating layer has at least one inclined surface extending obliquely upward, and
the gate insulating layer has an uppermost end or surface that is higher than an uppermost end or surface of the gate oxide layer.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a first body region by implanting first conductivity type impurities in the cell region using the gate electrode as a mask pattern; and
forming a source region by implanting second conductivity type impurities in the first body region.

### Claim 4 (depends on 2)

The method of claim 2, wherein the gate electrode has a lower surface that has a shape complementary to a shape of an upper surface of the gate insulating layer.

### Claim 5 (depends on 2)

The method of claim 2, wherein the gate insulating layer is in contact with the gate oxide layer at ends thereof.

### Claim 6 (depends on 2)

The method of claim 2, wherein the gate electrode has a center portion on the gate insulating layer and opposite ends or sides on the gate oxide layer.

### Claim 7 (depends on 2)

The method of claim 2, wherein the first conductivity type pillars are spaced apart from each other in a horizontal direction.

### Claim 8 (depends on 2)

The method of claim 2, wherein each of the field oxide layer and the gate insulating layer has an uppermost end or surface that is higher than an uppermost end or surface of the gate oxide layer.