# US 12,009,415 B2 · High electron mobility transistor and method for fabricating the same

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- Number: US 12,009,415 B2
- Document ID: US12009415B2
- Status: Granted
- Kind: B2
- Application number: 18/144,811
- Filed: 2023-05-08
- Published: 2023-08-31
- Granted: 2024-06-11
- Earliest claimed: 2020-07-21
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Kuo-Hsing Lee; Sheng-Yuan Hsueh; Chien-Liang Wu; Kuo-Yu Liao
- Web page: https://patentgrep.com/patent/US12009415B2

## CPC

- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 84/05: using Group III-V technology
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 1/68: Capacitors having no potential barriers
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a high electron mobility transistor (HEMT) region and a capacitor region;
a mesa isolation on the HEMT region;
a HEMT on the mesa isolation;
a capacitor on the capacitor region; and
a buffer layer between the mesa isolation, the capacitor, and the substrate, wherein a bottom electrode of the capacitor contacts the buffer layer directly.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein mesa isolation and the buffer layer comprise gallium nitride (GaN).

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the HEMT comprises:
a barrier layer on the mesa isolation;
a p-type semiconductor layer on the barrier layer;
a gate electrode on the p-type semiconductor layer;
a source electrode and a drain electrode adjacent to two sides of the gate electrode;
a source electrode extension on the source electrode; and
a drain electrode extension on the drain electrode.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising a hard mask on the mesa isolation and around the source electrode and the drain electrode.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the capacitor comprises:
the bottom electrode on the buffer layer;
a capacitor dielectric layer on the bottom electrode and extending to the hard mask on the HEMT region; and
a top electrode on the capacitor dielectric layer.

### Claim 6

A semiconductor device, comprising:
a substrate having a high electron mobility transistor (HEMT) region and a capacitor region;
a mesa isolation on the HEMT region;
a HEMT on the mesa isolation;
a hard mask around the HEMT and extending to the capacitor region, wherein a top surface of the hard mask on the capacitor region is lower than a top surface of the hard mask on the HEMT region; and
a capacitor on the hard mask.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising a buffer layer between the mesa isolation, the hard mask, and the substrate.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein mesa isolation and the buffer layer comprise gallium nitride (GaN).

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the HEMT comprises:
a barrier layer on the mesa isolation;
a p-type semiconductor layer on the barrier layer;
a gate electrode on the p-type semiconductor layer;
a source electrode and a drain electrode adjacent to two sides of the gate electrode;
a source electrode extension on the source electrode; and
a drain electrode extension on the drain electrode.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the hard mask surrounds the p-type semiconductor layer, the gate electrode, the source electrode, and the drain electrode.

### Claim 11 (depends on 6)

The semiconductor device of claim 6, wherein the capacitor comprises:
a bottom electrode on the hard mask;
a capacitor dielectric layer on the bottom electrode and extending to the hard mask on the HEMT region; and
a top electrode on the capacitor dielectric layer.