# US 12,009,412 B2 · Bipolar transistors

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- Number: US 12,009,412 B2
- Document ID: US12009412B2
- Status: Granted
- Kind: B2
- Application number: 17/549,013
- Filed: 2021-12-13
- Published: 2023-03-23
- Granted: 2024-06-11
- Earliest claimed: 2021-09-21
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GLOBALFOUNDRIES U.S. Inc.
- Inventors: Shesh Mani Pandey; Judson R. Holt; Vibhor Jain
- Web page: https://patentgrep.com/patent/US12009412B2

## CPC

- H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)}
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 10/01: Manufacture or treatment
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/311: {Thin-film BJTs}
- H10D 62/137: {Collector regions of BJTs}
- H10P 90/1912: {using selective deposition, e.g. epitaxial lateral overgrowth [ELO] or selective deposition of single crystal silicon}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a base region composed of a semiconductor on insulator material; an emitter region above the base region; and a collector region under the base region and within a cavity of a buried insulator layer.

## Claims

### Claim 1

A structure comprising:
a base region comprising a semiconductor on insulator material;
an emitter region above the base region and surrounded by an insulator material above the semiconductor on insulator material; and
a collector region of semiconductor material under the base region and within a cavity of a buried insulator layer,
wherein a bottom surface of the collector region is facing a portion of the buried insulator layer below the collector region and portions of the collector region extend upward into the insulator material and above a bottom surface of the emitter region.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the base region comprises SiGe material.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the emitter region comprises epitaxial semiconductor material on the base region.

### Claim 4 (depends on 1)

The structure of claim 1, wherein the collector region comprises epitaxial semiconductor material.

### Claim 5 (depends on 4)

The structure of claim 4, wherein the epitaxial semiconductor material comprises Si base material with an n-type dopant.

### Claim 6 (depends on 5)

The structure of claim 5, wherein the n-type dopant comprises a higher concentration at a bottom than at a top.

### Claim 7 (depends on 4)

The structure of claim 4, wherein the epitaxial semiconductor material completely fills the cavity and contacts an underside of the base region.

### Claim 8 (depends on 4)

The structure of claim 4, wherein the epitaxial semiconductor material partially fills the cavity and contacts an underside of the base region.

### Claim 9 (depends on 8)

The structure of claim 8, further comprising an airgap under the epitaxial semiconductor material.

### Claim 10 (depends on 4)

The structure of claim 4, wherein the buried insulator layer comprises a buried oxide layer under the semiconductor on insulator material, and the epitaxial semiconductor material of the collector region is surrounded by the buried oxide layer.

### Claim 11 (depends on 1)

The structure of claim 1, further comprising contacts to the emitter region, the base region and the collector region, and from a top down view the contacts to the emitter region and the base region are on a first axis perpendicular to the contacts to the collector region and emitter region on a second axis.

### Claim 12

A structure comprising:
a semiconductor on insulator substrate comprising a semiconductor handle substrate, a buried insulator material above the semiconductor handle substrate and a semiconductor layer above the buried insulator material;
a base region comprising the semiconductor layer and bounded by shallow trench isolation structures;
an emitter region vertically above the base region and bounded by an insulator material above the buried insulator material; and
a collector region of semiconductor material vertically below the base region and surrounded from above, below and sides by the buried insulator material and further extending into the insulation material on sides-of the base region and above a bottom surface the emitter region.

### Claim 13 (depends on 12)

The structure of claim 12, wherein the collector region comprises a doped semiconductor material within a cavity of the buried insulator material.

### Claim 14 (depends on 12)

The structure of claim 12, wherein the collector region comprises a doped semiconductor material partially filling a cavity of the buried insulator material.

### Claim 15 (depends on 14)

The structure of claim 14, further comprising an airgap under the doped semiconductor material.

### Claim 16 (depends on 12)

The structure of claim 12, wherein the buried insulator material is on sidewalls of the collector region.

### Claim 17 (depends on 12)

The structure of claim 12, wherein the collector region, the base region and the emitter region are vertically stacked.

### Claim 18 (depends on 12)

The structure of claim 12, wherein the semiconductor layer of the base region comprises SiGe.

### Claim 19 (depends on 12)

The structure of claim 12, wherein the semiconductor layer of the base region contacts a semiconductor material of the collector region.

### Claim 20

A method comprising:
forming a base region comprising a semiconductor on insulator material;
forming an emitter region above the base region and surrounded by an insulator material above the semiconductor on insulator material; and
forming a collector region of semiconductor material under the base region and within a cavity of a buried insulator layer, wherein a bottom surface of the collector region is facing a portion of the buried insulator layer below the collector region and portions of the collector region extend upward into the insulator material and above a bottom surface of the emitter region.