# US 12,009,411 B2 · Forming 3D transistors using 2D Van Der Waals materials

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- Number: US 12,009,411 B2
- Document ID: US12009411B2
- Status: Granted
- Kind: B2
- Application number: 17/874,377
- Filed: 2022-07-27
- Published: 2022-11-10
- Granted: 2024-06-11
- Earliest claimed: 2019-12-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Sheng-Kai Su; Jin Cai
- Web page: https://patentgrep.com/patent/US12009411B2

## CPC

- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- H10D 62/883: {Transition metal dichalcogenides, e.g. MoSe2}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a dielectric fin over a dielectric layer;
forming a ring encircling and contacting sidewalls of the dielectric fin, the ring comprising a two-dimensional semiconductor material, wherein the forming the ring comprises:
conformally depositing the two-dimensional semiconductor material; and
removing portions of the two-dimensional semiconductor material to form the ring;
forming a gate dielectric contacting top surfaces of the dielectric fin, the dielectric layer, and the two-dimensional semiconductor material;
forming a gate electrode over the gate dielectric; and
forming a source/drain contact plug contacting the two-dimensional semiconductor material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the ring comprises forming a MoS2 ring.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming the ring comprises forming a MoSe2 ring.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming spacers in physical contact with the gate dielectric.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming the dielectric fin forms the dielectric fin to a thickness of between about 20 nm and about 60 nm.

### Claim 6 (depends on 1)

The method of claim 1, wherein after the forming the source/drain contact plug, the source/drain contact plug contacts a top surface of the dielectric fin.

### Claim 7

A method of manufacturing a semiconductor device, the method comprising:
forming a dielectric layer;
forming a dielectric region;
forming a two-dimensional semiconductor material, wherein a first sidewall of the two-dimensional semiconductor material contacts the dielectric region to form a first vertical interface, wherein the dielectric layer is underlying and in contact with both the dielectric region and the two-dimensional semiconductor material;
forming a gate dielectric extending on tops of the dielectric region and the two-dimensional semiconductor material, and contacts a second sidewall of the two-dimensional semiconductor material;
forming a gate electrode on the gate dielectric; and
forming a source/drain contact plug contacting a third sidewall of the two-dimensional semiconductor material to form a second vertical interface, wherein the first sidewall and the third sidewall of the two-dimensional semiconductor material are opposite sidewalls, wherein the source/drain contact plug comprises a bottom surface contacting a top surface of the dielectric layer, wherein after the forming the source/drain contact plug, the source/drain contact plug contacts a top surface of the dielectric region.

### Claim 8 (depends on 7)

The method of claim 7, further comprising forming a gate spacer, wherein the source/drain contact plug further contacts an additional sidewall of the gate spacer.

### Claim 9 (depends on 7)

The method of claim 7, wherein the two-dimensional semiconductor material comprises a transition metal dichalcogenide material.

### Claim 10 (depends on 7)

The method of claim 7, wherein the two-dimensional semiconductor material is a mono layer material.

### Claim 11 (depends on 7)

The method of claim 7, wherein the two-dimensional semiconductor material comprises a plurality of monolayers.

### Claim 12 (depends on 7)

The method of claim 7, wherein the dielectric region and the dielectric layer are formed of different dielectric materials.

### Claim 13 (depends on 7)

The method of claim 7, wherein the forming the two-dimensional semiconductor material comprises forming a MoS2 layer.

### Claim 14

A method of manufacturing a semiconductor device, the method comprising:
forming a dielectric fin;
forming a transition metal dichalcogenide layer on sidewalls of the dielectric fin, wherein the transition metal dichalcogenide layer comprises a 2D material;
forming a gate dielectric contacting top surfaces of the dielectric fin, wherein the gate dielectric contacts a first portion of a sidewall of the transition metal dichalcogenide layer;
forming a gate electrode over the gate dielectric; and
forming a source/drain contact plug contacting a second portion of the sidewall of the transition metal dichalcogenide layer, wherein the source/drain contact plug is free of the 2D material.

### Claim 15 (depends on 14)

The method of claim 14, wherein the forming the transition metal dichalcogenide layer comprises forming a MoS2 layer.

### Claim 16 (depends on 14)

The method of claim 14, wherein the forming the transition metal dichalcogenide layer comprises forming a MoSe2 layer.

### Claim 17 (depends on 14)

The method of claim 14, wherein the forming the transition metal dichalcogenide layer comprises forming a WS2 layer.

### Claim 18 (depends on 14)

The method of claim 14, wherein the forming the transition metal dichalcogenide layer comprises forming a WSe2 layer.

### Claim 19 (depends on 14)

The method of claim 14, wherein the forming the transition metal dichalcogenide layer comprises:
conformally depositing a material for the transition metal dichalcogenide layer; and
etching the material for the transition metal dichalcogenide layer.

### Claim 20 (depends on 14)

The method of claim 14, wherein the forming the dielectric fin forms the dielectric fin to a thickness of between about 20 nm and about 60 nm.