# US 12,009,410 B2 · Semiconductor device and method fabricating the same

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- Number: US 12,009,410 B2
- Document ID: US12009410B2
- Status: Granted
- Kind: B2
- Application number: 18/301,712
- Filed: 2023-04-17
- Published: 2023-08-10
- Granted: 2024-06-11
- Earliest claimed: 2018-09-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Zhi-Chang Lin; Wei-Hao Wu; Jia-Ni Yu
- Web page: https://patentgrep.com/patent/US12009410B2

## CPC

- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/834: {comprising FinFETs}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a semiconductor fin extending along a first direction on the substrate;
a dielectric fin disposed on the substrate and extending substantially parallel to the semiconductor fin;
a gate structure across the semiconductor fin and the dielectric fin; and
gate spacers disposed on opposite sidewalls of the gate structure, wherein an interface between the gate structure and the dielectric fin is lower than an interface between the dielectric fin and one of the gate spacers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the interface between the gate structure and the dielectric fin is lower than a bottom segment of the ILD layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric fin has a first portion covered by the gate structure and two second portions on opposite sides of the first portion, respectively, wherein the second portions have a top surface higher than a top surface of the first portion.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor fin has a width less than a width of the dielectric fin.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a shallow trench isolation (STI) region on the substrate; and
a spacing layer spacing apart the dielectric fin from the STI region.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the spacing layer is made of a material same as a material of the STI region.

### Claim 7

A semiconductor device, comprising:
a substrate;
a semiconductor fin protruding from the substrate and extending along a first direction;
a first dielectric fin extending along the first direction, wherein the first dielectric fin has a bottom surface higher than a bottom of the semiconductor fin; and
a gate structure across the semiconductor fin and the first dielectric fin.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first dielectric fin has a width greater than a width of the semiconductor fin.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, further comprising:
a self-aligned-contact (SAC) layer on the gate structure.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, further comprising:
a second dielectric fin spaced apart from the first dielectric fin at least by the semiconductor fin.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the second dielectric fin has a top surface higher than a top surface of the first dielectric fin.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the top surface of the second dielectric fin is higher than a top surface of the gate structure.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, further comprising:
a self-aligned-contact (SAC) layer on the gate structure and the second dielectric fin, wherein the SAC layer is thicker over the gate structure than over the second dielectric fin.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the second dielectric fin has a bottom surface higher than the bottom of the semiconductor fin.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, further comprising:
gate spacers on either side of the gate structure, wherein the first dielectric fin has a first protruding portion interfacing inner sidewalls of the gate spacers, and the second dielectric fin has a second protruding portion interfacing inner sidewalls of the gate spacers.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the second protruding portion of the second dielectric fin has a height greater than a height of the first protruding portion of the first dielectric fin.

### Claim 17

A semiconductor device, comprising:
a substrate;
a plurality of semiconductor fins formed on the substrate and extending along a first direction;
an isolation fin over the substrate and extending along the first direction;
a plurality of hard masks respectively on the plurality of semiconductor fins, wherein the plurality of hard masks are formed as a same material as the isolation fin; and
a gate structure extending across the plurality of hard masks and the plurality of semiconductor fins.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein sidewalls of the plurality of semiconductor fins are free from coverage by the plurality of hard masks.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the isolation fin has a top at level with tops of the plurality of hard masks.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the tops of the plurality of hard masks are more rounded than the top of the isolation fin.