# US 12,009,408 B2 · Multi-gate devices having a semiconductor layer between an inner spacer and an epitaxial feature

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,009,408 B2
- Document ID: US12009408B2
- Status: Granted
- Kind: B2
- Application number: 17/870,292
- Filed: 2022-07-21
- Published: 2022-11-10
- Granted: 2024-06-11
- Earliest claimed: 2019-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wei Ju Lee; Chun-Fu Cheng; Chung-Wei Wu; Zhiqiang Wu
- Web page: https://patentgrep.com/patent/US12009408B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/6308: {of Group IV semiconductors}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/509: {characterised by the material of the inner spacers}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes channel members vertically stacked over a substrate, a gate structure engaging the channel members, a gate spacer layer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, an inner spacer layer interposing the gate structure and the epitaxial feature, and a semiconductor layer interposing the inner spacer layer and the epitaxial feature.

## Claims

### Claim 1

A semiconductor device, comprising:
channel members vertically stacked over a substrate;
a gate structure engaging the channel members;
a gate spacer layer disposed on sidewalls of the gate structure;
an epitaxial feature abutting the channel members;
an inner spacer layer interposing the gate structure and the epitaxial feature; and
a semiconductor layer interposing the inner spacer layer and the epitaxial feature.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor layer is embedded in the inner spacer layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor layer is in physical contact with the epitaxial feature.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the inner spacer layer surrounds lateral ends of the channel members, and wherein the lateral ends of the channel members have a thickness smaller than center portions of the channel members.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the inner spacer layer has a thickness measured in a vertical direction that is larger than a distance between two adjacent channel members.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein a ratio of the thickness and the distance ranges from about 1.1:1 to about 1.4:1.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor layer is in amorphous form.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the inner spacer layer is an oxide layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the inner spacer layer includes SiGeO.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the inner spacer layer is directly under the gate spacer layer, and the semiconductor layer is laterally offset from the gate spacer layer.

### Claim 11

A semiconductor device, comprising:
one or more channel layers over a substrate;
a gate structure engaging the one or more channel layers;
a source/drain (S/D) formation assistance region partially embedded in the substrate, wherein the S/D formation assistance region includes a semiconductor seed layer embedded in an isolation layer, and wherein the isolation layer electrically isolates the semiconductor seed layer from the substrate; and
an S/D epitaxial feature connecting to the semiconductor seed layer and the one or more channel layers.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein a bottom portion of the S/D formation assistance region has a width larger than a top portion of the S/D formation assistance region.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the isolation layer electrically isolates the S/D epitaxial feature from the gate structure.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the isolation layer is in physical contact with a top surface, a bottom surface, and a sidewall of the semiconductor seed layer.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the semiconductor seed layer is undoped.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein the one or more channel layers have terminal ends wrapped around by the isolation layer and middle portions wrapped around by the gate structure.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the terminal ends are thinner than the middle portions of the one or more channel layers.

### Claim 18

A semiconductor device, comprising:
channel members vertically stacked over a substrate;
a gate structure wrapping around each of the channel members;
an epitaxial feature abutting the channel members;
an isolation layer in physical contact with the epitaxial feature and the gate structure; and
a semiconductor layer in physical contact with the epitaxial feature and the isolation layer, wherein a top surface and a bottom surface of the semiconductor layer is covered by the isolation layer.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the epitaxial feature includes a first epitaxial layer in physical contact with the semiconductor layer and a second epitaxial layer surrounded by the first epitaxial layer, and wherein the first and second epitaxial layers include different dopant concentrations.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein the semiconductor layer has a thickness measured in a vertical direction that is smaller than a distance between two adjacent channel members.