# US 12,009,407 B2 · Nanosheet field-effect transistor device and method of forming

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- Number: US 12,009,407 B2
- Document ID: US12009407B2
- Status: Granted
- Kind: B2
- Application number: 18/303,841
- Filed: 2023-04-20
- Published: 2023-08-31
- Granted: 2024-06-11
- Earliest claimed: 2020-08-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wen-Kai Lin; Yung-Cheng Lu; Che-Hao Chang; Chi On Chui
- Web page: https://patentgrep.com/patent/US12009407B2

## CPC

- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/679: {comprising air gaps}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/3452: {Microstructure}
- H10P 50/283: {by chemical means}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
forming a gate structure over a nanostructure, wherein the nanostructure overlies a fin, wherein the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material;
forming openings in the nanostructure on opposing sides of the gate structure to expose end portions of the first semiconductor material and end portions of the second semiconductor material;
recessing the exposed end portions of the first semiconductor material to form first sidewall recesses;
filling the first sidewall recesses with a multi-layer spacer film, wherein the multi-layer spacer film comprises a first dielectric layer and a second dielectric layer different from the first dielectric layer;
removing a sublayer of the multi-layer spacer film to form second sidewall recesses, comprising:
performing a first etching process to remove first portions of the first dielectric layer and first portions of the second dielectric layer disposed outside the first sidewall recesses; and
after performing the first etching process, performing a second etching process to selectively remove the second dielectric layer, wherein the first etching process is a first dry etch process, and the second etching process is a second dry etch process performed using different etching gases; and
forming source/drain regions in the openings after removing the sublayer, wherein the source/drain regions seal the second sidewall recesses to form sealed air gaps.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first etching process is performed using a gas source comprising a mixture of CHF3 and O2, a mixture of CF4 and O2, or a mixture of NF3, CH3F, and CHF.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second etching process is performed using a gas source comprising NF3, NH3, or HF.

### Claim 4 (depends on 2)

The method of claim 2, wherein performing the first etching process comprises tuning parameters of the first etching process to adjust a lateral etching rate of the first etching process.

### Claim 5 (depends on 1)

The method of claim 1, wherein filling the first sidewall recesses comprises:
lining the openings and the first sidewall recesses with the first dielectric layer; and
after the lining, fill the first sidewall recesses with the second dielectric layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the second etching process is performed using an etchant selective to the second dielectric layer, wherein after the second etching process, remaining portions of the first dielectric layer in the first sidewall recesses form inner spacers.

### Claim 7 (depends on 1)

The method of claim 1, wherein a first dielectric constant of the first dielectric layer is higher than a second dielectric constant of the second dielectric layer.

### Claim 8 (depends on 7)

The method of claim 7, wherein a first atomic percentage of oxygen in the first dielectric layer is lower than a second atomic percentage of oxygen in the second dielectric layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein the second etching process removes the first dielectric layer at a first etch rate, and removes the second dielectric layer at a second etch rate, wherein the second etch rate is ten times or more than the first etch rate.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
after forming the source/drain regions, removing the gate structure to expose the first semiconductor material and the second semiconductor material disposed under the gate structure;
selectively removing the exposed first semiconductor material, wherein after selectively removing the exposed first semiconductor material, the second semiconductor material remains and forms a plurality of nanosheets; and
forming a replacement gate structure around the plurality of nanosheets.

### Claim 11 (depends on 10)

The method of claim 10, wherein forming the replacement gate structure comprises:
forming a gate dielectric material around the plurality of nanosheets; and
forming a gate electrode material around the gate dielectric material and the plurality of nanosheets.

### Claim 12

A method of forming a semiconductor device, the method comprising:
forming a first gate structure over a nanostructure, wherein the nanostructure comprises layers of a first semiconductor material interleaved with layers of a second semiconductor material, wherein the nanostructure is disposed over a fin;
forming recesses in the nanostructure on opposing sides of the first gate structure;
removing portions of the first semiconductor material exposed by the recesses to form first sidewall recesses;
lining the recesses and the first sidewall recesses with a multi-layer spacer film, wherein the multi-layered spacer film comprises a first spacer layer and a second spacer layer that are formed of different materials;
performing a first dry etch process to remove first portions of the first spacer layer and first portions of the second spacer layer that are disposed outside the first sidewall recesses; and
after performing the first dry etch process, performing a second dry etch process to remove second portions of the second spacer layer from the first sidewall recesses, wherein the first dry etch process and the second dry etch process are performed using different etching gases.

### Claim 13 (depends on 12)

The method of claim 12, wherein after performing the second dry etch process, second portions of the first spacer layer remain in the first sidewall recesses and form inner spacers.

### Claim 14 (depends on 13)

The method of claim 13, further comprising, after performing the second dry etch process, forming source/drain regions in the recesses, wherein the source/drain regions seal the first sidewall recesses to form air gaps.

### Claim 15 (depends on 12)

The method of claim 12, wherein the first spacer layer is formed in the first sidewall recesses and in physical contact with the first semiconductor material, wherein the second spacer layer is separated from the first semiconductor material by the first spacer layer.

### Claim 16 (depends on 12)

The method of claim 12, wherein the second dry etch process is performed using an etchant selective to the second spacer layer.

### Claim 17

A method of forming a semiconductor device, the method comprising:
forming a nanostructure over a fin, the nanostructure comprising alternating layers of a first semiconductor material and a second semiconductor material;
forming a first gate structure over the nanostructure;
forming source/drain openings extending into the nanostructure on opposing sides of the first gate structure;
recessing portions of the first semiconductor material exposed by the source/drain openings to form first sidewall recesses;
conformally and successively forming a first spacer layer and a second spacer layer in the source/drain openings and in the first sidewall recesses;
performing a trimming process to remove first portions of the first spacer layer and first portions of the second spacer layer disposed outside the first sidewall recesses, wherein the trimming process is an etching process performed using a first etchant;
after performing the trimming process, performing a cleaning process, wherein the cleaning process selectively removes second portions of the second spacer layer disposed in the first sidewall recesses, wherein the cleaning process is a dry etch process performed using a second etchant different from the first etchant; and
forming source/drain regions in the source/drain openings, wherein air gaps are formed between the source/drain regions and remaining portions of the first spacer layer in the first sidewall recesses.

### Claim 18 (depends on 17)

The method of claim 17, wherein the trimming process is another dry etch process different from the dry etch process of the cleaning process.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first etchant is a first gas source, and the second etchant is a second gas source different from the first gas source.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first spacer layer is formed of a first dielectric material having a first dielectric constant, and the second spacer layer is formed of a second dielectric material having a second dielectric constant smaller than the first dielectric constant.