# US 12,009,404 B2 · Semiconductor devices

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- Number: US 12,009,404 B2
- Document ID: US12009404B2
- Status: Granted
- Kind: B2
- Application number: 17/686,504
- Filed: 2022-03-04
- Published: 2022-06-16
- Granted: 2024-06-11
- Earliest claimed: 2018-07-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Seungseok Ha; Gukil An; Keun Hwi Cho; Sungmin Kim
- Web page: https://patentgrep.com/patent/US12009404B2

## CPC

- H10D 30/6744: {Monocrystalline silicon}
- H10D 64/689: {having ferroelectric layers}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate including an active pattern;
a device isolation layer on the substrate and in a trench that defines the active pattern;
a plurality of semiconductor patterns that are stacked on the active pattern and are spaced apart from each other in a vertical direction;
a plurality of ferroelectric patterns on the plurality of semiconductor patterns, respectively; and
a gate electrode on the plurality of ferroelectric patterns,
wherein, in a cross-sectional view taken along a longitudinal direction of the gate electrode:
the plurality of ferroelectric patterns are spaced apart from each other in the vertical direction,
each of the plurality of ferroelectric patterns is between the gate electrode and a respective one of the plurality of semiconductor patterns,
each of the plurality of ferroelectric patterns surrounds a respective one of the plurality of semiconductor patterns,
the gate electrode includes a work function metal pattern and an electrode pattern,
the work function metal pattern is in a space between adjacent ones of the plurality of ferroelectric patterns, and
the space between the adjacent ones of the plurality of ferroelectric patterns is free of the electrode pattern.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the work function metal pattern encloses the plurality of ferroelectric patterns.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising a plurality of interface layers, each of which is between a respective one of the plurality of semiconductor patterns and a respective one of the plurality of ferroelectric patterns.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of ferroelectric patterns includes a lowermost ferroelectric pattern, and
wherein the lowermost ferroelectric pattern is between the gate electrode and the device isolation layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein each of the plurality of ferroelectric patterns comprises hafnium oxide that comprises zirconium (Zr), silicon (Si), aluminum (Al) and/or lanthanum (La).

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the work function metal pattern comprises a titanium nitride layer and/or a tantalum nitride layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein each of the plurality of ferroelectric patterns extends on a surface of a respective one of the plurality of semiconductor patterns.

### Claim 8

A semiconductor device comprising:
a substrate including an active pattern;
a device isolation layer on the substrate and in a trench that defines the active pattern;
first, second and third semiconductor patterns that are sequentially stacked on the active pattern and spaced apart from each other in a vertical direction;
a source/drain pattern connected to the first, second and third semiconductor patterns;
a first ferroelectric pattern between the active pattern and the first semiconductor pattern, a second ferroelectric pattern between the first semiconductor pattern and the second semiconductor pattern, and a third ferroelectric pattern between the second semiconductor pattern and the third semiconductor pattern;
a gate electrode on the first, second and third ferroelectric patterns; and
first, second and third inner spacers between the source/drain pattern and the first, second and third ferroelectric patterns, respectively,
wherein the first, second and third ferroelectric patterns directly contact the first, second and third inner spacers, respectively.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein each of the first, second and third ferroelectric patterns defines a space therein, and
wherein the gate electrode includes a work function metal pattern in the spaces.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the gate electrode further includes an electrode pattern, and
wherein the electrode pattern is not in the spaces.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the work function metal pattern comprises a titanium nitride layer and/or a tantalum nitride layer.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein a top surface of the source/drain pattern is higher than a top surface of the third semiconductor pattern.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, further comprising an active contact electrically connected to the source/drain pattern,
wherein the source/drain pattern includes a recess in an upper portion thereof, and
wherein a lower portion of the active contact is in the recess.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein each of the first, second and third ferroelectric patterns comprises hafnium oxide that comprises zirconium (Zr), silicon (Si), aluminum (Al) and/or lanthanum (La).

### Claim 15

A semiconductor device comprising:
a substrate including a first active pattern and a second active pattern;
a device isolation layer on the substrate and in a trench that is between the first and second active patterns;
a plurality of first semiconductor patterns that are stacked on the first active pattern and spaced apart from each other in a vertical direction;
a first source/drain pattern connected to the plurality of first semiconductor patterns;
a plurality of second semiconductor patterns that are stacked on the second active pattern and spaced apart from each other in the vertical direction;
a second source/drain pattern connected to the plurality of second semiconductor patterns;
a first ferroelectric pattern on the plurality of first semiconductor patterns;
a second ferroelectric pattern on the plurality of second semiconductor patterns;
an inner spacer between the second ferroelectric pattern and the second source/drain pattern;
a first gate electrode on the first ferroelectric pattern; and
a second gate electrode on the second ferroelectric pattern,
wherein the first ferroelectric pattern directly contacts the first source/drain pattern, and
wherein the second ferroelectric pattern is spaced apart from the second source/drain pattern by the inner spacer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the first source/drain pattern comprises silicon-germanium (SiGe).

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the first source/drain pattern and the second source/drain pattern have different conductivity types.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein a top surface of the first source/drain pattern is higher than a top surface of an uppermost one of the plurality of first semiconductor patterns.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, further comprising an active contact electrically connected to the first source/drain pattern,
wherein the first source/drain pattern includes a recess in an upper portion thereof, and
wherein a lower portion of the active contact is in the recess.