# US 12,009,403 B2 · Semiconductor structure with metal cap layer and method for manufacturing the same

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- Number: US 12,009,403 B2
- Document ID: US12009403B2
- Status: Granted
- Kind: B2
- Application number: 17/830,059
- Filed: 2022-06-01
- Published: 2022-09-15
- Granted: 2024-06-11
- Earliest claimed: 2019-05-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chung-Liang Cheng; Ziwei Fang
- Web page: https://patentgrep.com/patent/US12009403B2

## CPC

- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/0111: {to Group IV semiconductors}
- H10D 64/01304: {characterised by the conductor}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/432: {using selective deposition}
- H10P 14/6528: {In-situ cleaning after layer formation, e.g. removing process residues}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10P 70/27: {during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10P 14/6314: {of a metallic layer}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a fin protruding from a substrate and a gate stack formed across the fin. The semiconductor structure further includes a source/drain structure attaching to the gate stack and a contact structure connecting to the source/drain structure. The semiconductor structure further includes a first cap layer covering a top surface of the contact structure. In addition, the first cap layer includes a first halogen.

## Claims

### Claim 1

A semiconductor structure, comprising:
a fin protruding from a substrate;
a gate stack formed across the fin;
a source/drain structure attaching to the gate stack;
a contact structure connecting to the source/drain structure; and
a first cap layer covering a top surface of the contact structure, wherein the first cap layer comprises a first halogen.

### Claim 2 (depends on 1)

The semiconductor structure as claimed in claim 1, further comprising:
sidewall spacers interposed the gate stack and the contact structure, wherein the first cap layer physically contacts the sidewall spacers.

### Claim 3 (depends on 1)

The semiconductor structure as claimed in claim 1, further comprising:
a first mask layer formed over the first cap layer; and
a conductive structure formed through the first mask layer,
wherein an interface between the first mask layer and the first cap layer is substantially level with an interface between the conductive structure and the first cap layer.

### Claim 4 (depends on 3)

The semiconductor structure as claimed in claim 3, further comprising:
a second mask layer formed over the gate stack, wherein a portion of the second mask layer vertically sandwiched between the conductive structure and the gate stack.

### Claim 5 (depends on 4)

The semiconductor structure as claimed in claim 4, wherein a top surface of the second mask layer is lower than a top surface of the first mask layer.

### Claim 6 (depends on 3)

The semiconductor structure as claimed in claim 3, further comprising:
sidewall spacers sandwiched between the gate stack and the contact structure, wherein the conductive structure physically contacts a top surface and a sidewall surface of the sidewall spacers.

### Claim 7 (depends on 1)

The semiconductor structure as claimed in claim 1, further comprising:
a second cap layer formed over the gate stack, wherein the second cap layer comprise a second halogen different from the first halogen.

### Claim 8 (depends on 7)

The semiconductor structure as claimed in claim 7, wherein the gate stack comprises:
a gate dielectric layer; and
a gate electrode layer formed over the gate dielectric layer,
wherein the second cap layer physically contact a sidewall of the gate dielectric layer and covers a top surface of the gate electrode layer.

### Claim 9 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein a top surface of the gate dielectric layer is higher than an interface between the second cap layer and the gate electrode layer.

### Claim 10 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein a top surface of the gate dielectric layer is lower than a top surface of the second cap layer.

### Claim 11

A method for forming a semiconductor structure, comprising:
patterning a substrate to form a fin;
forming a source/drain structure attaching to the fin;
forming a contact structure over the source/drain structure; and
introducing a first halogen-containing precursor on a top surface of the contact structure to form a first cap layer.

### Claim 12 (depends on 11)

The method for forming a semiconductor structure as claimed in claim 11, wherein the first cap layer comprises the first halogen.

### Claim 13 (depends on 11)

The method for forming a semiconductor structure as claimed in claim 11, further comprising:
forming a gate stack over the fin adjacent to the source/drain structure; and
introducing a second halogen-containing precursor on a top surface of the gate stack to form a second cap layer.

### Claim 14 (depends on 13)

The method for forming a semiconductor structure as claimed in claim 13, wherein the second cap layer comprises the second halogen different from the first halogen.

### Claim 15 (depends on 14)

The method for forming a semiconductor structure as claimed in claim 14, wherein the first cap layer and the second cap layer comprise a same metal.

### Claim 16

A method for forming a semiconductor structure, comprising:
forming a fin protruding from a substrate;
forming a source/drain structure over the fin;
forming a gate stack over the fin;
recessing the gate stack to form a first recess;
forming a first halogen-containing cap layer at a bottom portion of the first recess; and
forming a first mask layer in the first recess.

### Claim 17 (depends on 16)

The method for forming a semiconductor structure as claimed in claim 16, further comprising:
forming a contact structure over the source/drain structure;
recessing the contact structure to form a second recess;
forming a second halogen-containing cap layer at a bottom portion of the second recess; and
forming a second mask layer in the second recess,
wherein the first halogen-containing cap layer and the second halogen-containing cap layer comprises different halogens.

### Claim 18 (depends on 17)

The method for forming a semiconductor structure as claimed in claim 17, further comprising:
forming a first trench through the first mask layer to expose the first halogen-containing cap layer; and
forming a first conductive structure in the first trench,
wherein a portion of the first conductive structure vertically overlaps the contact structure and is separated from the contact structure by the second mask layer.

### Claim 19 (depends on 17)

The method for forming a semiconductor structure as claimed in claim 17, further comprising:
forming a second trench through the second mask layer to expose the second halogen-containing cap layer; and
forming a second conductive structure in the second trench,
wherein a portion of the second conductive structure vertically overlaps the first mask layer.

### Claim 20 (depends on 17)

The method for forming a semiconductor structure as claimed in claim 17, wherein the second mask layer covers a top surface of the first mask layer.