# US 12,009,401 B2 · Memory transistor with multiple charge storing layers and a high work function gate electrode

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- Number: US 12,009,401 B2
- Document ID: US12009401B2
- Status: Granted
- Kind: B2
- Application number: 17/952,796
- Filed: 2022-09-26
- Published: 2023-01-26
- Granted: 2024-06-11
- Earliest claimed: 2007-05-25
- Assignees: Longitude Flash Memory Solutions Ltd.
- Applicants: Longitude Flash Memory Solutions Ltd.
- Inventors: Igor Polishchuk; Sagy Charel Levy; Krishnaswamy Ramkumar
- Web page: https://patentgrep.com/patent/US12009401B2

## CPC

- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/00: EEPROM devices comprising charge-trapping gate insulators
- H10B 43/30: characterised by the memory core region
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10D 64/683: {being parallel to the channel plane}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

## Claims

### Claim 1

A memory device, comprising:
at least one vertical string of non-planar multigate memory transistor devices;
each non-planar multigate memory transistor device including a channel region extending along a length of the at least one vertical string;
said channel region connecting a first diffusion region and a second diffusion region of the non-planar multigate memory transistor; and
said memory device having a gate-all-around (GAA) structure in which the channel region is enclosed on sides by a gate.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein a second memory string includes a second tunnel dielectric layer surrounding a second channel region, a second multi-layer charge storing region surround the second tunnel dielectric, and a second blocking dielectric layer surrounding the second multi-layer charge storing region.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein a first vertical memory string includes a tunnel dielectric layer surrounding the channel region, a multi-layer charge storing region surround the tunnel dielectric, and a blocking dielectric layer surrounding the multi-layer charge storing region.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the blocking dielectric layer includes a high K dielectric.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein the channel region, the tunnel dielectric later and the multi-layer charge storing region are each formed in a substantially annular shape.

### Claim 6 (depends on 3)

The memory device of claim 3, wherein the multi-layer charge storing region includes a first oxygen-lean nitride layer and a second oxygen-rich nitride layer.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the first oxygen-lean nitride layer and the second oxygen-rich nitride layer both include silicon, nitrogen and oxygen components.

### Claim 8 (depends on 6)

The memory device of claim 6, wherein the first vertical memory string further includes an anti-tunneling layer between the first oxygen-lean nitride layer and the second oxygen-rich nitride layer.

### Claim 9 (depends on 6)

The memory device of claim 6, wherein the first oxygen-lean nitride layer is oxygen-lean relative to the second oxygen-rich nitride layer.

### Claim 10

A memory device, comprising:
a semiconductor material;
a first vertical memory string projecting from the semiconductor material, the first vertical memory string including a first channel extending along a length of the first vertical memory string from a first diffusion region to a second diffusion region;
a second vertical memory string projecting from the semiconductor material, the second vertical memory string including a second channel extending along a length of the second vertical memory string from the first diffusion region to the second diffusion region; and
a gate structure surrounding both a portion of the first vertical memory string and a portion of the second vertical memory string.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the second vertical memory string includes a second tunnel dielectric layer surrounding a second channel region, a second multi-layer charge storing region surround the second tunnel dielectric, and a second blocking dielectric layer surrounding the second multi-layer charge storing region.

### Claim 12 (depends on 10)

The memory device of claim 10, wherein the gate is a gate all around structure that encloses the first and second vertical memory strings.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the first channel connects the first and second diffusion regions.

### Claim 14 (depends on 10)

The memory device of claim 10, wherein the first vertical memory string includes a tunnel dielectric layer surrounding a first channel region, a multi-layer charge storing region surround the tunnel dielectric, and a blocking dielectric layer surrounding the multi-layer charge storing region.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the blocking dielectric layer includes a high K dielectric.

### Claim 16 (depends on 14)

The memory device of claim 14, wherein a channel region, the tunnel dielectric layer and the multi-layer charge storing region are each formed in a substantially annular shape.

### Claim 17 (depends on 14)

The memory device of claim 14, wherein the multi-layer charge storing region includes a first oxygen-lean nitride layer and a second oxygen-rich nitride layer.

### Claim 18 (depends on 17)

The memory device of claim 17, wherein the first oxygen-lean nitride layer and the second oxygen-rich nitride layer both include silicon, nitrogen and oxygen components.

### Claim 19 (depends on 17)

The memory device of claim 17, wherein the first vertical memory string further includes an anti-tunneling layer between the first oxygen-lean nitride layer and the second oxygen-rich nitride layer.

### Claim 20 (depends on 17)

The memory device of claim 17, wherein the first oxygen-lean nitride layer is oxygen-lean relative to the second oxygen-rich nitride layer.