# US 12,009,399 B2 · Semiconductor device suppressing rounded shapes of source/drain contact layers

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- Number: US 12,009,399 B2
- Document ID: US12009399B2
- Status: Granted
- Kind: B2
- Application number: 17/222,100
- Filed: 2021-04-05
- Published: 2021-07-22
- Granted: 2024-06-11
- Earliest claimed: 2015-11-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yi-Jyun Huang; Tung-Heng Hsieh; Bao-Ru Young
- Web page: https://patentgrep.com/patent/US12009399B2

## CPC

- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 64/01: Manufacture or treatment
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0153: {using gate cut processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/282: {of inorganic materials}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a first fin structure extending in a first direction and having a source/drain region;
an isolation insulating layer, from which an upper portion of the first fin structure protrudes;
an interlayer dielectric layer disposed over the isolation insulating layer;
a first source/drain contact layer disposed on the source/drain region of the first fin structure and extending in a second direction crossing the first direction, a part of the first source/drain contact layer being disposed over the isolation insulating layer; and
a separation insulating layer disposed adjacent to the first source/drain contact layer, wherein:
an end of the first source/drain contact layer is in contact with a first face of the separation insulating layer, and
the separation insulating layer is made of an insulating material different from the isolation insulating layer and the interlayer dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first source/drain contact layer includes at least one of W, Co, Ni, Ti, and Ta, a silicide thereof and a nitride thereof.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the insulating material of the separation insulating layer is SiN.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising a conductive plug on the separation insulating layer and the first source/drain contact layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second fin structure extending in the first direction and having a source/drain region; and
a second source/drain contact layer disposed on the source/drain region of the second fin structure at a location opposite to the first source/drain contact layer,
wherein the separation insulating layer is disposed between the first source/drain contact layer and the second source/drain contact layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein an end of the second source/drain contact layer is in contact with a second face of the separation insulating layer opposite to the first face.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, further comprising:
a first gate electrode disposed over the first fin structure and extending in the second direction,
wherein an end of the first gate electrode is in contact with the first face of the separation insulating layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising:
a second gate electrode disposed over the second fin structure and extending in the second direction, wherein:
the first gate electrode is aligned with the second gate electrode in the second direction, and
an end of the second gate electrode is in contact with the second face of the separation insulating layer.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, further comprising:
a second gate electrode disposed over the first fin structure and extending in the second direction, wherein:
the first source/drain contact layer is disposed between the first gate electrode and the second gate electrode, and
an end of the second gate electrode is in contact with the first face of the separation insulating layer.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second fin structure extending in the first direction and having a source/drain region,
wherein the first source/drain contact layer is disposed on the source/drain region of the second fin structure.

### Claim 11

A semiconductor device, comprising:
a first fin structure and a second fin structure isolated from the first fin structure by an isolation insulating layer, the first and second fin structures extending in a first direction;
a first gate electrode and a second gate electrode, the first and second gate electrodes disposed over the first fin and second fin structures and extending in a second direction crossing the first direction;
a first source/drain contact layer disposed over and in electrically contact with the first and second fin structures, and between the first gate electrode and second gate electrode; and
a separation insulating layer disposed adjacent to the first source/drain contact layer, wherein:
the first source/drain contact layer is in contact with a first side face of the separation insulating layer, and
the separation insulating layer is made of silicon nitride.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein a part of the first source/drain contact layer is in contact with the isolation insulating layer.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, further comprising an interlayer dielectric layer disposed over the first and second fin structures,
wherein an insulating material of the separation insulating layer is different from an insulating material of the interlayer dielectric layer.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein an upper surface of the separation insulating layer is flush with an upper surface of the first source/drain contact layer.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, further comprising a conductive plug in contact with the separation insulating layer and the first source/drain contact layer.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein:
the first source/drain contact layer includes at least one of W, Co, Ni, Ti, and Ta, a silicide thereof and a nitride thereof, and
the separation insulating layer is made of SiN.

### Claim 17

A semiconductor device, comprising:
a first fin structure and a second fin structure;
a first gate structure and a second gate structure, both formed over the first fin structure;
a first source/drain contact layer disposed between the first gate structure and the second gate structure;
a third gate structure and a fourth gate structure, both formed over the second fin structure;
a second source/drain contact layer disposed between the third gate structure and the fourth gate structure;
a separation insulating layer separating the first source/drain contact layer from the second source/drain contact layer, wherein:
the first and second source/drain contact layers include at least one of W, Co, Ni, Ti, and Ta, a silicide thereof and a nitride thereof,
an end of the first gate structure, an end of the second gate structure and an end of the first source drain contact layer are in contact with a first side face of the separation insulating layer, and
an end of the third gate structure, an end of the fourth gate structure and an end of the second source drain contact layer are in contact with a second side face of the separation insulating layer opposite to the first side face.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising:
a first conductive plug disposed on the first source/drain contact layer; and
a second conductive plug disposed on the second source/drain contact layer.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, further comprising:
an interlayer dielectric layer disposed on the separation insulating layer and the first and second source/drain contact layers,
wherein the first conductive plug is separated by the second conductive plug by the interlayer dielectric layer.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein:
the first and second fin structures extend in a first direction and the first and second gate structures extend in a second direction crossing the first direction, and
a width of the separation isolation insulating layer in the first direction is greater than a distance between an outer side face of the first gate structure and an outer side face of the second gate structure.