# US 12,009,398 B2 · Semiconductor devices and methods of fabricating the same

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- Number: US 12,009,398 B2
- Document ID: US12009398B2
- Status: Granted
- Kind: B2
- Application number: 17/932,851
- Filed: 2022-09-16
- Published: 2023-01-12
- Granted: 2024-06-11
- Earliest claimed: 2020-01-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hyun-Seung Song; Tae-Yeol Kim; Jae-Jik Baek
- Web page: https://patentgrep.com/patent/US12009398B2

## CPC

- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 64/01: Manufacture or treatment
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/42: Vias, e.g. via plugs
- H10D 64/0112: {using conductive layers comprising silicides}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/047: {by introducing additional elements therein}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

## Claims

### Claim 1

A method of fabricating a semiconductor device, the method comprising
forming a first active pattern on a substrate;
forming a source/drain pattern on the first active pattern;
forming a gate electrode on the first active pattern;
forming an interlayer insulating layer on the gate electrode and the source/drain pattern;
forming a contact hole to penetrate the interlayer insulating layer and to expose the source/drain pattern;
forming a lower contact pattern in a lower portion of the contact hole;
forming a sacrificial layer on the lower contact pattern in the contact hole;
removing a portion of the sacrificial layer to form a sacrificial pattern including a first opening;
forming a mold pattern in the first opening; and
replacing the sacrificial pattern with an upper contact pattern.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first opening is formed to expose a top surface of the lower contact pattern.

### Claim 3 (depends on 1)

The method of claim 1, wherein the replacing of the sacrificial pattern with the upper contact pattern comprises:
selectively etching the sacrificial pattern in the contact hole to form a second opening; and
forming a conductive layer in the second opening.

### Claim 4 (depends on 1)

The method of claim 1, wherein the forming of the lower contact pattern in the lower portion of the contact hole comprises:
forming a preliminary contact pattern in the contact hole; and
removing an upper portion of the preliminary contact pattern.

### Claim 5 (depends on 1)

The method of claim 1, wherein the sacrificial pattern comprises an amorphous carbon layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein replacing the sacrificial pattern with the upper contact pattern comprises:
forming a second barrier pattern; and
forming a second conductive pattern on the second barrier pattern.

### Claim 7 (depends on 6)

The method of claim 6, wherein the second barrier pattern contacts the lower contact pattern.

### Claim 8 (depends on 6)

The method of claim 6, wherein the lower contact pattern comprises a first conductive pattern and a first barrier pattern that is on side and bottom surfaces of the first conductive pattern.

### Claim 9 (depends on 8)

The method of claim 8, wherein a thickness of the second barrier pattern is different from a thickness of the first barrier pattern.

### Claim 10 (depends on 1)

The method of claim 1, wherein the mold pattern includes silicon oxide, silicon nitride, or silicon oxynitride.

### Claim 11 (depends on 1)

The method of claim 1, further comprising forming a gate contact on the gate electrode,
wherein the upper contact pattern and the gate contact horizontally overlap each other.

### Claim 12 (depends on 11)

The method of claim 11, wherein the gate contact is formed through a separate process from that for the upper contact pattern.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
forming a first via on the upper contact pattern; and
forming a second via on the gate contact,
wherein the first via and the second via horizontally overlap each other.

### Claim 14

A method of fabricating a semiconductor device, the method comprising
forming a first active pattern on a substrate;
forming a source/drain pattern on the first active pattern;
forming a gate electrode on the first active pattern;
forming an interlayer insulating layer on the gate electrode and the source/drain pattern;
forming a contact hole to penetrate the interlayer insulating layer and to expose the source/drain pattern;
forming a lower contact pattern in a lower portion of the contact hole;
forming a sacrificial pattern on the lower contact pattern in the contact hole;
replacing the sacrificial pattern with an upper contact pattern; and
forming a gate contact on the gate electrode,
wherein the upper contact pattern and the gate contact horizontally overlap each other.

### Claim 15 (depends on 14)

The method of claim 14, wherein replacing the sacrificial pattern with the upper contact pattern comprises:
forming a second barrier pattern; and
forming a second conductive pattern on the second barrier pattern.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second barrier pattern contacts the lower contact pattern.

### Claim 17 (depends on 15)

The method of claim 15, wherein the lower contact pattern comprises a first conductive pattern and a first barrier pattern that is on side and bottom surfaces of the first conductive pattern.

### Claim 18 (depends on 17)

The method of claim 17, wherein a thickness of the second barrier pattern is different from a thickness of the first barrier pattern.

### Claim 19 (depends on 14)

The method of claim 14, wherein the gate contact is formed through a separate process from that for the upper contact pattern.

### Claim 20 (depends on 14)

The method of claim 14, further comprising:
forming a first via on the upper contact pattern; and
forming a second via on the gate contact,
wherein the first via and the second via horizontally overlap each other.