# US 12,009,397 B2 · Semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,009,397 B2
- Document ID: US12009397B2
- Status: Granted
- Kind: B2
- Application number: 17/539,772
- Filed: 2021-12-01
- Published: 2022-10-06
- Granted: 2024-06-11
- Earliest claimed: 2021-04-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Deok Han Bae; Ju Hun Park; Myung Yoon Um
- Web page: https://patentgrep.com/patent/US12009397B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device including a field insulating layer, a part of which protrudes upwardly in a vertical direction on an element isolation region between a first active region and a second active region may be provided.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate including a first region and a second region, the second region being adjacent to the first region in a first horizontal direction;
a first active pattern extending in a second horizontal direction on the first region, the second horizontal direction being different from the first horizontal direction;
a second active pattern extending in the second horizontal direction on the second region, the second active pattern being spaced apart from the first active pattern in the first horizontal direction;
a field insulating layer surrounding at least a part of side walls of each of the first and second active patterns on the substrate, the field insulating layer including a protrusion protruding upwardly in a vertical direction on a boundary line between the first region and the second region;
a gate electrode extending in the first horizontal direction on the first and second active patterns;
a first source/drain region on at least one side of the gate electrode on the first active pattern;
a second source/drain region on at least one side of the gate electrode on the second active pattern; and
a source/drain contact electrically connecting the first source/drain region and the second source/drain region with each other, the source/drain contact including a first portion and a second portion, the first portion extending toward the field insulating layer between the first source/drain region and the second source/drain region, the second portion on the first portion,
wherein a lower surface of the first portion of the source/drain contact includes a recess which is recessed upwardly in the vertical direction, and
at least a part of the protrusion is inside the recess.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein an upper end of the protrusion is lower than an upper surface of the first active pattern that is in contact with the first source/drain region.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising:
an interlayer insulating layer surrounding the first source/drain region and the source/drain contact on the field insulating layer; and
an etching stop layer being between the field insulating layer and the interlayer insulating layer, and being between the first source/drain region and the interlayer insulating layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the etching stop layer is between the protrusion and the recess.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the lower surface of the first portion of the source/drain contact is in contact with a part of the etching stop layer that is on an upper surface of the field insulating layer and adjacent to the protrusion.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein
an upper surface of the first active pattern that is in contact with the first source/drain region, and
an upper end of the protrusion is higher than the upper surface of the first active pattern.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first portion of the source/drain contact is in contact with the protrusion.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the lower surface of the first portion of the source/drain contact is in contact with a part of an upper surface of the field insulating layer that is adjacent to the protrusion.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein
the field insulating layer includes,
a first upper surface between the first active pattern and the protrusion, and
a second upper surface between the second active pattern and the protrusion, and
the second upper surface of the field insulating layer is higher than the first upper surface of the field insulating layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein
the first portion of the source/drain contact includes a first lower surface and a second lower surface, the first lower surface facing the first upper surface of the field insulating layer, the second lower surface facing the second upper surface of the field insulating layer, and
the second lower surface of the first portion of the source/drain contact is higher than the first lower surface of the first portion of the source/drain contact.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein
the source/drain contact further includes a third portion that protrudes upwardly in the vertical direction from the second portion of the source/drain contact, and
a width of the third portion of the source/drain contact in the second horizontal is narrower than a width of the second portion of the source/drain contact in the first horizontal direction.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first plurality of nanosheets stacked to be spaced apart from each other in the vertical direction on the first active pattern; and
a second plurality of nanosheets stacked to be spaced apart from each other in the vertical direction on the second active pattern,
wherein the gate electrode surrounds each of the first plurality of nanosheets and each of the second plurality of nanosheets.

### Claim 13

A semiconductor device comprising:
a substrate;
a first active region extending in a first horizontal direction on the substrate;
a second active region extending in the first horizontal direction on the substrate, the second active region spaced apart from the first active region in a second horizontal direction, the second horizontal direction being different from the first horizontal direction;
an element isolation region between the first active region and the second active region;
a field insulating layer being on the element isolation region and surrounding at least a part of side walls of the first and second active regions, the field insulating layer including a protrusion protruding upwardly in a vertical direction;
a first source/drain region on the first active region;
a second source/drain region on the second active region;
a source/drain contact electrically connecting the first source/drain region and the second source/drain region with each other, the source/drain contact including a first portion and a second portion, the first portion extending toward the field insulating layer on the element isolation region, the second portion on the first portion;
an interlayer insulating layer surrounding the first source/drain region and the source/drain contact on the field insulating layer; and
an etching stop layer being between the field insulating layer and the interlayer insulating layer, and being between the first source/drain region and the interlayer insulating layer,
wherein at least a part of the protrusion extends into the first portion of the source/drain contact.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein
a lower surface of the first portion of the source/drain contact includes a recess being recessed upwardly in the vertical direction, and
at least a part of the protrusion is inside the recess.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein a lower surface of the first portion of the source/drain contact is lower than a lower surface of the first source/drain region.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein the etching stop layer is between the protrusion and the source/drain contact.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, wherein the first portion of the source/drain contact is in contact with the protrusion.

### Claim 18 (depends on 13)

The semiconductor device of claim 13, wherein
the field insulating layer includes,
a first upper surface between the first active region and the protrusion, and
a second upper surface between the second active region and the protrusion, and
the second upper surface of the field insulating layer is higher than the first upper surface of the field insulating layer.

### Claim 19

A semiconductor device comprising:
a substrate including an NMOS region and a PMOS region, the PMOS region adjacent to the NMOS region in a first horizontal direction;
a first active pattern extending in a second horizontal direction on the NMOS region, the second horizontal direction being different from the first horizontal direction;
a second active pattern extending in the second horizontal direction on the PMOS region, the second active pattern being spaced apart from the first active pattern in the first horizontal direction;
a field insulating layer surrounding at least a part of side walls of each of the first and second active patterns on the substrate, the field insulating layer including a protrusion protruding upwardly in a vertical direction on a boundary line between the NMOS region and the PMOS region;
a gate electrode extending in the first horizontal direction on the first and second active patterns;
a first source/drain region on at least one side of the gate electrode on the first active pattern;
a second source/drain region on at least one side of the gate electrode on the second active pattern;
a source/drain contact electrically connecting the first source/drain region and second source/drain region with each other, the source/drain contact including a first portion and a second portion, the first portion extending toward the field insulating layer between the first source/drain region and the second source/drain region, the second portion on the first portion;
an interlayer insulating layer surrounding the first source/drain region and the source/drain contact on the field insulating layer; and
an etching stop layer being between the field insulating layer and the interlayer insulating layer, and being between the first source/drain region and the interlayer insulating layer,
wherein an upper end of the protrusion is lower than an upper surface of the first active pattern that is in contact with the first source/drain region,
a lower surface of the first portion of the source/drain contact includes a recess that is recessed upwardly in the vertical direction, and
at least a part of the protrusion is in contact with the first portion of the source/drain contact inside the recess.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the lower surface of the first portion of the source/drain contact is in contact with a part of an upper surface of the field insulating layer that is adjacent to the protrusion.