# US 12,009,395 B2 · Self-aligned block for vertical FETs

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- Number: US 12,009,395 B2
- Document ID: US12009395B2
- Status: Granted
- Kind: B2
- Application number: 17/404,014
- Filed: 2021-08-17
- Published: 2023-02-23
- Granted: 2024-06-11
- Earliest claimed: 2021-08-17
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruilong Xie; Junli Wang; Choonghyun Lee; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US12009395B2

## CPC

- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/853: {comprising FinFETs}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/837: {comprising vertical IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A vertical FET includes a channel fin between a bottom source/drain (S/D) region and a top S/D region, a gate upon a sidewall of the channel fin, a top metallization upon the top S/D region, a first contact metallization connected to the gate, a second contact metallization connected to the bottom S/D region, a first vertical liner between a portion of the gate and the first contact metallization, and a second vertical liner between the top metallization and the second contact metallization. The vertical FET may be fabricated by forming a self-aligned block and utilizing the self-aligned block to e.g., prevent gate to gate shorting during replacement gate formation or processing.

## Claims

### Claim 1

A semiconductor device comprising:
a channel fin between a bottom source/drain (S/D) region and a top S/D region;
a gate around the channel fin, the gate comprising a first gate portion directly connected to a first side of the channel fin and a second gate portion directly connected to a second side of the channel fin, the first gate portion comprising a first sidewall and a second sidewall, and the second gate portion comprising a third sidewall;
a top metallization upon the top S/D region;
a first contact metallization connected to the first sidewall of the gate;
a second contact metallization connected to the bottom S/D region;
a vertical liner comprising a first vertical liner portion directly connected to at least the second sidewall of the gate and directly connected to a sidewall of the first contact metallization and a second vertical liner portion directly connected to at least the third sidewall of the gate and directly connected to a sidewall of the second contact metallization; and
a top spacer between the gate and the top S/D region and in direct contact with the channel fin, the top spacer comprising a first sidewall that is in direct contact with the first vertical liner portion and a second sidewall that is in direct contact with the second vertical liner portion.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
an inner spacer below the second vertical liner portion and that is directly connected the third sidewall of the gate and that is directly connected to the sidewall of the second contact metallization.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising:
a bottom spacer below the inner spacer, between the second contact metallization and the channel fin, and between the gate and the bottom S/D region.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of top metallization is below a top surface of the first contact metallization and is below a top surface of the second contact metallization.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein respective sidewalls of the top S/D region directly contact the first vertical liner portion and the second vertical liner portion.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein respective sidewalls of the top metallization directly contact the first vertical liner portion and the second vertical liner portion.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the vertical liner is coplanar with a top surface of the first contact metallization and is coplanar with a top surface of the second contact metallization.

### Claim 8

A semiconductor device comprising:
a pFET comprising: a pFET channel fin between a pFET bottom source/drain (S/D) region and a pFET top S/D region; a pFET gate upon around the pFET channel fin, the pFET gate comprising a first pFET gate portion directly connected to a first side of the pFET channel fin and a second pFET gate portion directly connected to a second side of the pFET channel fin, the first pFET gate portion comprising a first pFET gate sidewall and a second pFET gate sidewall, and the second pFET gate portion comprising a third pFET gate sidewall; a pFET top metallization upon the pFET top S/D region; a pFET contact metallization connected to the pFET bottom S/D region; and a pFET vertical liner directly connected the third pFET gate sidewall and directly connected to a sidewall of the pFET contact metallization;
a nFET comprising: a nFET channel fin between a nFET bottom S/D region and a nFET top S/D region; a nFET gate around the nFET channel fin, the nFET gate comprising a first nFET gate portion directly connected to a first side of the nFET channel fin and a second nFET gate portion directly connected to a second side of the nFET channel fin, the first nFET gate portion comprising a first nFET gate sidewall and a second nFET gate sidewall, and the second nFET gate portion comprising a third nFET gate sidewall; a nFET top metallization upon the nFET top S/D region; a nFET contact metallization connected to the nFET bottom S/D region; and a nFET vertical liner directly connected a first sidewall of the nFET gate and directly connected to a sidewall of the nFET contact metallization;
a shared contact metallization connected to the first sidewall of the pFET gate and connected to the first sidewall of the nFET gate;
a shared vertical liner in direct contact with at least the second sidewall of the pFET gate, in direct contact with the shared contact metallization, and in direct contact with at least the second sidewall of the nFET gate; and
a shared top spacer around the pFET channel around the nFET channel and in direct contact with the shared vertical liner.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising:
a pFET inner spacer below the pFET vertical liner and that is directly connected to the third sidewall of the pFET gate and that is directly connected to the sidewall of the pFET contact metallization; and
a nFET inner spacer below the nFET vertical liner and that is directly connected to the third sidewall of the nFET gate and that is directly connected to the sidewall of the nFET contact metallization.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising:
a pFET bottom spacer below the pFET inner spacer and between the pFET contact metallization and the pFET channel fin; and
a nFET bottom spacer below the nFET inner spacer and between the nFET contact metallization and the nFET channel fin.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein a top surface of pFET top metallization is below a top surface of the pFET contact metallization and is below a top surface of the shared contact metallization, wherein a top surface of nFET top metallization is below a top surface of the nFET contact metallization and is below the top surface of the shared contact metallization.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein respective sidewalls of the pFET top S/D region physically contact the pFET vertical liner and the shared vertical liner and wherein respective sidewalls of the nFET top S/D region physically contact the nFET vertical liner and the shared vertical liner.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein respective sidewalls of the pFET top metallization physically contact the pFET vertical liner and the shared vertical liner, and wherein respective sidewalls of the nFET top metallization physically contact the nFET vertical liner and the shared vertical liner.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein a top surface of the shared vertical liner is coplanar with a top surface of the shared contact metallization, wherein a top surface of the pFET vertical liner is coplanar with a top surface of the pFET top metallization, and wherein a top surface of the nFET vertical liner is coplanar with a top surface of the nFET top metallization.