# US 12,009,394 B2 · Source/drain contacts and methods of forming same

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- Number: US 12,009,394 B2
- Document ID: US12009394B2
- Status: Granted
- Kind: B2
- Application number: 18/083,792
- Filed: 2022-12-19
- Published: 2023-04-20
- Granted: 2024-06-11
- Earliest claimed: 2020-06-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Li-Zhen Yu; Huan-Chieh Su; Lin-Yu Huang; Cheng-Chi Chuang; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12009394B2

## CPC

- H10D 30/6729: {characterised by the electrodes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3462: {Nanowires}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 50/283: {by chemical means}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/427: {Power or ground buses}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 64/0112: {using conductive layers comprising silicides}
- H10W 20/076: {in via holes or trenches}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

## Claims

### Claim 1

A device comprising:
a device layer comprising a first transistor;
a first interconnect structure on a front-side of the device layer; and
a second interconnect structure on a backside of the device layer, the second interconnect structure comprising:
a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a gate stack of the first transistor; and
a source/drain contact extending through the first dielectric layer to a source/drain region of the first transistor, wherein the source/drain contact electrically connects the source/drain region to a power rail in the second interconnect structure.

### Claim 2 (depends on 1)

The device of claim 1, wherein the semiconductor material is further disposed between the first dielectric layer and the source/drain region.

### Claim 3 (depends on 1)

The device of claim 1 further comprising a dielectric liner between the first dielectric layer and the device layer, wherein the dielectric liner is disposed along sidewalls of the source/drain contact.

### Claim 4 (depends on 3)

The device of claim 3, wherein the dielectric liner contacts a gate stack of the first transistor.

### Claim 5 (depends on 3)

The device of claim 3 further comprising an insulating spacer on a sidewall of the source/drain contact, wherein the insulating spacer is disposed between the dielectric liner and the source/drain contact.

### Claim 6 (depends on 5)

The device of claim 5, wherein the insulating spacer contacts the semiconductor material, and wherein the semiconductor material is disposed between the dielectric liner and the insulating spacer.

### Claim 7 (depends on 5)

The device of claim 5 further comprising a void between the insulating spacer and the dielectric liner.

### Claim 8 (depends on 5)

The device of claim 5 further comprising an insulating material between the insulating spacer and the dielectric liner, wherein the insulating material contacts the insulating spacer.

### Claim 9

A device comprising:
a device layer comprising a transistor; and
a backside interconnect structure on a backside of the device layer, the backside interconnect structure comprising:
a semiconductor material;
a first insulating material, wherein the first insulating material contacts a gate stack of the transistor and the semiconductor material;
a contact extending through the first insulating material to a first source/drain region in the device layer; and
a conductive line electrically connected to the first source/drain region by the contact.

### Claim 10 (depends on 9)

The device of claim 9, wherein the semiconductor material has a surface in a <111> crystalline plane.

### Claim 11 (depends on 9)

The device of claim 9 further comprising a void between the contact and the first insulating material.

### Claim 12 (depends on 9)

The device of claim 9 further comprising a second insulating material between the contact and the first insulating material.

### Claim 13 (depends on 9)

The device of claim 9 further comprising an insulating spacer on sidewalls of the contact, the insulating spacer separates the contact from the first insulating material.

### Claim 14 (depends on 13)

The device of claim 13 further comprising:
a second source/drain region in the device layer, wherein the first source/drain region and the second source/drain region are disposed on opposing sides of the gate stack; and
an epitaxial material between the second source/drain region and the first insulating material, wherein the semiconductor material is further disposed on a sidewall of the epitaxial material.

### Claim 15

A method comprising:
forming a device layer on a semiconductor substrate, the device layer comprising a plurality of transistors, wherein forming the device layer comprises:
etching a first recess in the semiconductor substrate;
epitaxially growing a sacrificial semiconductor material in the first recess; and
epitaxially growing a first source/drain region over the sacrificial semiconductor material in the first recess; and
forming a backside interconnect structure on a backside of the device layer, wherein forming the backside interconnect structure comprises:
removing a portion of semiconductor substrate to expose the sacrificial semiconductor material;
depositing a first dielectric layer over remaining portions of the semiconductor substrate and around the sacrificial semiconductor material;
removing the sacrificial semiconductor material to expose the first source/drain region, wherein the remaining portions of the semiconductor substrate masks a second source/drain region while removing the sacrificial semiconductor material; and
after removing the sacrificial semiconductor material, forming a source/drain contact to first source/drain region.

### Claim 16 (depends on 15)

The method of claim 15, wherein removing the portion of the semiconductor substrate further exposes a gate stack of the device layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the device layer further comprises:
etching a second recess in the semiconductor substrate;
epitaxially growing a semiconductor material in the first recess and the second recess, wherein the semiconductor material is epitaxially grown on the sacrificial semiconductor material in the first recess; and
epitaxially growing the second source/drain region in the second recess and over the semiconductor material.

### Claim 18 (depends on 17)

The method of claim 17 further comprising removing the remaining portions of the semiconductor substrate in the first recess before forming the source/drain contact and after removing the sacrificial semiconductor material.

### Claim 19 (depends on 17)

The method of claim 17 further comprising replacing the remaining portions of the semiconductor substrate in the first recess with a dielectric material before forming the source/drain contact and after removing the sacrificial semiconductor material.

### Claim 20 (depends on 17)

The method of claim 17 further comprising forming an insulating spacer on sidewalls of the first recess before forming the source/drain contact.