# US 12,009,389 B2 · Edge termination for power semiconductor devices and related fabrication methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,389 B2 - Document ID: US12009389B2 - Status: Granted - Kind: B2 - Application number: 17/538,026 - Filed: 2021-11-30 - Published: 2023-06-01 - Granted: 2024-06-11 - Earliest claimed: 2021-11-30 - Assignees: Wolfspeed, Inc. - Applicants: Wolfspeed, Inc. - Inventors: Woongsun Kim; Daniel Jenner Lichtenwalner; Sei-Hyung Ryu; Naeem Islam - Web page: https://patentgrep.com/patent/US12009389B2 ## CPC - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 30/0291: {of vertical DMOS [VDMOS] FETs} - H10D 30/665: {having edge termination structures} - H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)} - H10D 62/8325: {Silicon carbide} - H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10P 30/22: using masks - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A power semiconductor device includes semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type. The guard rings extend into a surface of the semiconductor drift region. The guard rings respectively comprise a first portion adjacent the surface and a second portion spaced from the surface, where the first portion is wider than the second portion. Related devices and fabrication methods are also discussed. ## Claims ### Claim 1 A power semiconductor device, comprising: a semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type, wherein one or more of the guard rings extend in the semiconductor drift region to a depth of greater than about 1 micrometers (μm) relative to a surface of the semiconductor layer structure, and two or more of the guard rings are laterally separated from one another by a spacing of less than about 3 μm. ### Claim 2 (depends on 1) The power semiconductor device of claim 1, wherein the one or more of the guard rings respectively comprise a first portion adjacent the surface and a second portion spaced from the surface, wherein the first portion is wider than the second portion. ### Claim 3 (depends on 2) The power semiconductor device of claim 2, wherein the second portion comprises a higher concentration of dopants of the second conductivity type than the first portion. ### Claim 4 (depends on 2) The power semiconductor device of claim 2, wherein the first portion extends into the surface to a first depth, and wherein the second portion extends through the first portion to a second depth that is greater than the first depth. ### Claim 5 (depends on 2) The power semiconductor device of claim 2, wherein the one or more of the guard rings respectively comprise a third portion comprising a higher concentration of dopants of the second conductivity type than the second portion. ### Claim 6 (depends on 5) The power semiconductor device of claim 5, wherein the third portion is narrower than the first portion. ### Claim 7 (depends on 5) The power semiconductor device of claim 5, wherein the third portion is confined within the first portion in two or more dimensions. ### Claim 8 (depends on 2) The power semiconductor device of claim 2, wherein the one or more of the guard rings respectively comprise a sidewall comprising a step difference between the first and second portions. ### Claim 9 (depends on 4) The power semiconductor device of claim 4, wherein the semiconductor layer structure further comprises an active region comprising a plurality of well regions of the second conductivity type in the semiconductor drift region, wherein the well regions extend to the first depth. ### Claim 10 (depends on 9) The power semiconductor device of claim 9, wherein the active region further comprises a plurality of shielding patterns comprising a higher concentration of dopants of the second conductivity type than the well regions, wherein the shielding patterns extend to the second depth. ### Claim 11 (depends on 2) The power semiconductor device of claim 2, wherein the spacing is substantially uniform between the first portions. ### Claim 12 (depends on 1) The power semiconductor device of claim 1, wherein the depth is about 1 μm to about 3 μm, and wherein the spacing is about 0.5 lam to about 3 μm. ### Claim 13 (depends on 1) The power semiconductor device of claim 1, wherein the one or more of the guard rings respectively comprise a first width adjacent the surface and a second width spaced from the surface, and wherein a ratio of the first width to the second width is about 0.95 to about 2. ### Claim 14 A power semiconductor device, comprising: a semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type in the semiconductor drift region, wherein one or more of the guard rings respectively comprise a first portion adjacent a surface of the semiconductor layer structure and a second portion spaced from the surface of the semiconductor layer structure, wherein the second portion comprises a higher concentration of dopants of the second conductivity type than the first portion. ### Claim 15 (depends on 14) The power semiconductor device of claim 14, wherein the first portion is wider than the second portion. ### Claim 16 (depends on 15) The power semiconductor device of claim 15, wherein the first portion extends into the surface to a first depth, and wherein the second portion extends through the first portion and to a second depth that is greater than the first depth. ### Claim 17 (depends on 15) The power semiconductor device of claim 15, wherein the one or more of the guard rings respectively comprise a third portion comprising a higher concentration of dopants of the second conductivity type than the second portion, wherein the third portion is narrower than the first portion. ### Claim 18 (depends on 14) The power semiconductor device of claim 14, wherein two or more of the guard rings are laterally separated from one another by a spacing, wherein the spacing is substantially uniform between the first portions. ### Claim 19 A power semiconductor device, comprising: a semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type in the semiconductor drift region, wherein one or more of the guard rings respectively comprise a first portion adjacent a surface of the semiconductor layer structure, a second portion spaced from the surface of the semiconductor layer structure, and a sidewall, wherein the sidewall of a respective guard ring comprises a step difference between the first and second portions. ### Claim 20 (depends on 19) The power semiconductor device of claim 19, wherein the second portion comprises a higher concentration of dopants of the second conductivity type than the first portion, and wherein the step difference is defined at an interface between the first and second portions. ### Claim 21 (depends on 20) The power semiconductor device of claim 20, wherein the first portion is wider than the second portion. ### Claim 22 (depends on 20) The power semiconductor device of claim 20, wherein the first portion extends into the surface to a first depth, and wherein the second portion extends through the first portion to a second depth that is greater than the first depth. ### Claim 23 (depends on 22) The power semiconductor device of claim 22, wherein the semiconductor layer structure further comprises an active region comprising a plurality of well regions of the second conductivity type in the semiconductor drift region, wherein the well regions extend to the first depth. ### Claim 24 (depends on 23) The power semiconductor device of claim 23, wherein the active region further comprises a plurality of shielding patterns comprising a higher concentration of dopants of the second conductivity type than the well regions, wherein the shielding patterns extend to the second depth. ### Claim 25 A power semiconductor device, comprising: a semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type in the semiconductor drift region, wherein one or more of the guard rings respectively comprise a first width adjacent a surface of the semiconductor layer structure and a second width spaced from the surface of the semiconductor layer structure, and wherein a ratio of the first width to the second width is about 0.95 to about 2. ### Claim 26 (depends on 25) The power semiconductor device of claim 25, wherein the one or more of the guard rings respectively comprise a first portion comprising the first width between outermost boundaries thereof and a second portion comprising the second width between outermost boundaries thereof, wherein the first portion is wider than the second portion. ### Claim 27 (depends on 26) The power semiconductor device of claim 26, wherein the second portion comprises a higher concentration of dopants of the second conductivity type than the first portion. ### Claim 28 (depends on 26) The power semiconductor device of claim 26, wherein the first portion extends into the surface to a first depth, and wherein the second portion extends through the first portion to a second depth that is greater than the first depth. ### Claim 29 (depends on 26) The power semiconductor device of claim 26, wherein the one or more of the guard rings respectively comprise a third portion comprising a higher concentration of dopants of the second conductivity type than the second portion, wherein the third portion is narrower than the first portion. ### Claim 30 (depends on 26) The power semiconductor device of claim 26, wherein the one or more of the guard rings respectively comprise a sidewall comprising a step difference between the first and second portions. ### Claim 31 (depends on 25) The power semiconductor device of claim 25, wherein the ratio is about 0.95 to about 1.05. ### Claim 32 (depends on 25) The power semiconductor device of claim 25, wherein the ratio is about 0.99 to about 1.01.