# US 12,009,387 B2 · Integrated circuit device and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,387 B2 - Document ID: US12009387B2 - Status: Granted - Kind: B2 - Application number: 17/323,433 - Filed: 2021-05-18 - Published: 2021-09-02 - Granted: 2024-06-11 - Earliest claimed: 2019-02-20 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jun-goo Kang; Hyun-suk Lee; Gi-hee Cho - Web page: https://patentgrep.com/patent/US12009387B2 ## CPC - H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)} - H10B 12/033: {the capacitor extending over the transistor} - H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug} - H10B 12/31: {having a storage electrode stacked over the transistor} - H10D 1/042: {using deposition processes to form electrode extensions} - H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching} - H10D 1/692: {Electrodes} - H10D 1/714: {having horizontal extensions} - H10D 1/716: {having vertical extensions} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part. ## Claims ### Claim 1 An integrated circuit device comprising: a substrate; an insulating interlayer on the substrate; an etch stop layer on the insulating interlayer; a lower electrode structure disposed over the insulating interlayer; a dielectric layer disposed on the lower electrode structure; and an upper electrode disposed on the dielectric layer, wherein the lower electrode structure includes a first lower electrode, a second lower electrode that is disposed on the first lower electrode, and a third lower electrode that is disposed on the second lower electrode, a bottom surface of the second lower electrode of the lower electrode structure contacts a top surface of the first lower electrode of the lower electrode structure, the dielectric layer contacts the first lower electrode, the second lower electrode and the third lower electrode of the lower electrode structure, and an outer bottommost point of the dielectric layer is below a topmost surface of the insulating interlayer. ### Claim 2 (depends on 1) The integrated circuit device according to claim 1, wherein the third lower electrode of the lower electrode structure contacts an inner side surface, an inner bottom surface and a top surface of the second lower electrode of the lower electrode structure. ### Claim 3 (depends on 1) The integrated circuit device according to claim 1, wherein the second lower electrode of the lower electrode structure includes at least one of niobium nitride, niobium oxide, or niobium oxynitride. ### Claim 4 (depends on 1) The integrated circuit device according to claim 1, wherein the dielectric layer includes hafnium oxide. ### Claim 5 (depends on 1) The integrated circuit device according to claim 1, wherein the lower electrode structure includes a fourth lower electrode that is the same material as the first lower electrode and the third lower electrode of the lower electrode structure. ### Claim 6 (depends on 5) The integrated circuit device according to claim 5, further comprising a supporting layer that is disposed over the substrate, wherein the fourth lower electrode of the lower electrode structure is disposed between the second lower electrode of the lower electrode structure and the supporting layer. ### Claim 7 (depends on 1) The integrated circuit device according to claim 1, wherein the second lower electrode of the lower electrode structure is cylinder-shaped with an upper opened end, and the third lower electrode of the lower electrode structure is cylinder-shaped with a filled interior. ### Claim 8 (depends on 1) The integrated circuit device according to claim 1, wherein the third lower electrode of the lower electrode structure includes a first portion that is in contact with an inner bottom surface and an inner side surface of the second lower electrode of the lower electrode structure, and a second portion that is disposed on the first portion. ### Claim 9 (depends on 8) The integrated circuit device according to claim 8, wherein a bottom surface of the second portion of the third lower electrode of the lower electrode structure contacts a top surface of the second lower electrode of the lower electrode structure. ### Claim 10 (depends on 8) The integrated circuit device according to claim 8, wherein a width of the first portion of the third lower electrode of the lower electrode structure is less than a width of the second portion of the third lower electrode of the lower electrode structure. ### Claim 11 (depends on 8) The integrated circuit device according to claim 8, wherein the first portion of the third lower electrode of the lower electrode structure is spaced apart from the dielectric layer, and the second portion of the third lower electrode of the lower electrode structure contacts the dielectric layer. ### Claim 12 (depends on 1) The integrated circuit device according to claim 1, further comprising: a contact plug disposed in the insulating interlayer, wherein the first lower electrode of the lower electrode structure passes through the etch stop layer and contacts the contact plug, and the dielectric layer passes through the etch stop layer and contacts the contact plug. ### Claim 13 (depends on 8) The integrated circuit device according to claim 8, further comprising a supporting layer that is disposed over the substrate, wherein the supporting layer contacts a side surface of the second portion of the third lower electrode of the lower electrode structure. ### Claim 14 (depends on 5) The integrated circuit device according to claim 5, wherein the third lower electrode of the lower electrode structure is spaced apart from the first lower electrode of the lower electrode structure, and contacts the second lower electrode and the fourth lower electrode of the lower electrode structure. ### Claim 15 An integrated circuit device comprising: a substrate; an insulating interlayer on the substrate; an etch stop layer on the insulating interlayer; a lower electrode structure disposed over the insulating interlayer; a dielectric layer disposed on the lower electrode structure; and an upper electrode disposed on the dielectric layer, wherein the lower electrode structure includes a first lower electrode, a second lower electrode that is disposed on the first lower electrode, and a third lower electrode that is disposed on the second lower electrode, a bottom surface of the second lower electrode of the lower electrode structure contacts a top surface of the first lower electrode of the lower electrode structure, the third lower electrode of the lower electrode structure includes a first portion that is in contact with an inner bottom surface and an inner side surface of the second lower electrode of the lower electrode structure, and a second portion that is disposed on the first portion, a bottom surface of the second portion of the third lower electrode of the lower electrode structure contacts a top surface of the second lower electrode of the lower electrode structure, an outer bottommost point of the dielectric layer is below a topmost surface of the insulating interlayer, and a width of the first portion of the third lower electrode of the lower electrode structure is less than a width of the second portion of the third lower electrode of the lower electrode structure. ### Claim 16 (depends on 15) The integrated circuit device according to claim 15, wherein the dielectric layer contacts the first lower electrode, the second lower electrode and the third lower electrode of the lower electrode structure. ### Claim 17 (depends on 15) The integrated circuit device according to claim 15, wherein the second lower electrode of the lower electrode structure includes at least one of niobium, nitride, niobium oxide, or niobium oxynitride, and the dielectric layer includes hafnium oxide. ### Claim 18 (depends on 15) The integrated circuit device according to claim 15, the first portion of the third lower electrode of the lower electrode structure is spaced apart from the dielectric layer, and the second portion of the third lower electrode of the lower electrode structure contacts the dielectric layer. ### Claim 19 An integrated circuit device comprising: a substrate; an insulating interlayer disposed on the substrate; an etch stop layer disposed on the insulating interlayer; a contact plug disposed in the insulating interlayer; a lower electrode structure disposed on the contact plug; a dielectric layer disposed on the lower electrode structure and including hafnium oxide; and an upper electrode disposed on the dielectric layer, wherein the lower electrode structure includes a first lower electrode, a second lower electrode that is disposed on the first lower electrode, and a third lower electrode that is disposed on the second lower electrode, the second lower electrode of the lower electrode structure includes at least one of niobium, nitride, niobium oxide, or niobium oxynitride, the first lower electrode of the lower electrode structure passes through the etch stop layer and contacts the contact plug, an outer bottommost point of the dielectric layer is below a topmost surface of the insulating interlayer, a bottom surface of the second lower electrode of the lower electrode structure contacts a top surface of the first lower electrode of the lower electrode structure, the third lower electrode of the lower electrode structure includes a first portion that is in contact with an inner bottom surface and an inner side surface of the second lower electrode of the lower electrode structure, and a second portion that is disposed on the first portion, a bottom surface of the second portion of the third lower electrode of the lower electrode structure contacts a top surface of the second lower electrode of the lower electrode structure, a width of the first portion of the third lower electrode of the lower electrode structure is less than a width of the second portion of the third lower electrode of the lower electrode structure, the first portion of the third lower electrode of the lower electrode structure is spaced apart from the dielectric layer, and the second portion of the third lower electrode of the lower electrode structure contacts the dielectric layer. ### Claim 20 (depends on 19) The integrated circuit device according to claim 19, wherein the dielectric layer contacts the first lower electrode, the second lower electrode and the third lower electrode.