# US 12,009,366 B2 · Array substrate, manufacturing method thereof, and display device

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- Number: US 12,009,366 B2
- Document ID: US12009366B2
- Status: Granted
- Kind: B2
- Application number: 16/970,808
- Filed: 2020-06-12
- Published: 2023-04-20
- Granted: 2024-06-11
- Earliest claimed: 2020-05-12
- Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Inventors: Xiaohui Nie
- Web page: https://patentgrep.com/patent/US12009366B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 86/021: {of multiple TFTs}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)}
- G09G 2330/12: Test circuits or failure detection circuits included in a display system, as permanent part thereof
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a terminal region. A testing electric circuit wiring is disposed in the terminal region. The testing electric circuit wiring includes a first metal layer, a second metal layer, and a third metal layer.

## Claims

### Claim 1

An array substrate, comprising a terminal region,
wherein a testing electric circuit wiring is disposed in the terminal region, and the terminal region comprises a pixel electrode,
wherein the testing electric circuit wiring comprises:
a first metal layer configured to act as a light shielding layer and a signal transmitting line for a testing electric current of the testing electric circuit wiring;
a second metal layer configured to act as a gate electrode wiring, to transmit the testing electric current to gate electrodes; and
a third metal layer configured to act as a testing electric circuit, wherein the third metal layer is electrically connected to the pixel electrode, and the testing electric current is capable of transmitting between the third metal layer and the pixel electrode;
wherein the second metal layer is connected to the first metal layer, and
the third metal layer is connected to the first metal layer.

### Claim 2 (depends on 1)

The array substrate as claimed in claim 1, wherein the array substrate comprises:
a base substrate, wherein the first metal layer is disposed on a surface of a side of the base substrate, and the first metal layer is a winding-type;
a buffer layer disposed on a surface of a side of the first metal layer away from the base substrate;
an insulating layer disposed on a surface of a side of the buffer layer away from the first metal layer;
the second metal layer disposed on a surface of a side of the buffer layer away from the first metal layer;
a dielectric layer disposed on a surface of a side of the second metal layer away from the buffer layer; and
the third metal layer disposed on a surface of a side of the dielectric layer away from the buffer layer.

### Claim 3 (depends on 2)

The array substrate as claimed in claim 2, wherein
a plurality of buffer layer via holes are defined on the buffer layer;
a plurality of insulating layer via holes are defined on the insulating layer;
the plurality of insulating layer via holes and the plurality of buffer layer via holes are defined relatively;
a plurality of dielectric layer via holes are defined on the dielectric layer; and
the plurality of dielectric layer via holes and the plurality of insulating layer via holes are defined relatively.

### Claim 4 (depends on 3)

The array substrate as claimed in claim 3, wherein
one of the buffer layer via holes and one of the insulating layer via holes defined relatively are communicated with each other to form a first via hole, and
another one of the buffer layer via holes, another one of the insulating layer via holes, and one of the dielectric layer via holes defined relatively are communicated with each other to form a second via hole.

### Claim 5 (depends on 3)

The array substrate as claimed in claim 3, wherein
internal diameters of the buffer layer via holes are less than internal diameters of the insulating layer via holes; and
the internal diameters of the insulating layer via holes are less than internal diameters of the dielectric layer via holes.

### Claim 6 (depends on 5)

The array substrate as claimed in claim 5, wherein
the second metal layer is partially disposed in the first via hole and connected to the first metal layer; and
the third metal layer is partially disposed in the second via hole and connected to the first metal layer.

### Claim 7 (depends on 1)

Manufacturing method of an array substrate for manufacturing the array substrate as claimed in claim 1, comprising following steps:
providing a base substrate in a step of providing the base substrate;
manufacturing a first metal layer on a top surface of the base substrate in a step of manufacturing the first metal layer, wherein the first metal layer is a winding-type;
manufacturing a buffer layer on a top surface of the first metal layer in a step of manufacturing the buffer layer;
manufacturing an insulating layer on a top surface of the buffer layer in a step of manufacturing the insulating layer;
manufacturing a second metal layer on a top surface of the insulating layer in a step of manufacturing the second metal layer;
manufacturing a dielectric layer on a top surface of the second metal layer in a step of manufacturing the dielectric layer; and
manufacturing a third metal layer on a top surface of the dielectric layer in a step of manufacturing the third metal layer, wherein the third metal layer, the second metal layer, and the first metal layer constitute a testing electric circuit wiring.

### Claim 8 (depends on 7)

The manufacturing method of the array substrate as claimed in claim 7, wherein
in the step of manufacturing the buffer layer,
a layer of a buffer material is deposited on the top surface of the first metal layer, at least one buffer layer via hole is defined by using exposure and etching technology, and part of the first metal layer is exposed in the buffer layer via hole;
in the step of manufacturing the insulating layer,
a layer of an insulation material is deposited on the top surface of the buffer layer, at least one insulating layer via hole is defined on the buffer layer via hole by using the exposure and etching technology, the insulating layer via hole is communicated with the buffer layer via hole, and the insulating layer via hole and the buffer layer via hole form a first via hole; and
in the step of manufacturing the second metal layer,
the second metal layer is manufactured in the first via hole, and the second metal layer is connected to the first metal layer.

### Claim 9 (depends on 8)

The manufacturing method of the array substrate as claimed in claim 8, wherein
in the step of manufacturing the dielectric layer,
a layer of an inorganic material is deposited on the top surfaces of the insulating layer and the second metal layer, a dielectric layer via hole is defined on the insulating layer via hole by using the exposure and etching technology, the dielectric layer via hole is communicated with the insulating layer via hole, and the dielectric layer via hole, the insulating layer via hole, and the buffer layer via hole form a second via hole; and
in the step of manufacturing the third metal layer,
the third metal layer is manufactured in the second via hole, and the third metal layer is connected to the first metal layer.

### Claim 10

A display device, comprising an array substrate comprising a terminal region,
wherein a testing electric circuit wiring is disposed in the terminal region, and the terminal region comprises a pixel electrode,
wherein the testing electric circuit wiring comprises:
a first metal layer configured to act as a light shielding layer and a signal transmitting line for a testing electric current of the testing electric circuit wiring;
a second metal layer configured to act as a gate electrode wiring, to transmit the testing electric current to gate electrodes; and
a third metal layer configured to act as a testing electric circuit, wherein the third metal layer is electrically connected to the pixel electrode, and the testing electric current is capable of transmitting between the third metal layer and the pixel electrode;
wherein the second metal layer is connected to the first metal layer, and
the third metal layer is connected to the first metal layer.