# US 12,009,363 B2 · Method for forming source/drain contacts

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,009,363 B2
- Document ID: US12009363B2
- Status: Granted
- Kind: B2
- Application number: 17/347,066
- Filed: 2021-06-14
- Published: 2021-10-07
- Granted: 2024-06-11
- Earliest claimed: 2017-11-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shao-Ming Koh; Chen-Ming Lee; Fu-Kai Yang; Mei-Yun Wang
- Web page: https://patentgrep.com/patent/US12009363B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/853: {comprising FinFETs}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 50/242: {of Group IV materials}
- H10P 50/282: {of inorganic materials}
- H10P 50/287: {by chemical means}
- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10P 70/20: {Cleaning during device manufacture}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/071: {of dielectric parts thereof}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/0112: {using conductive layers comprising silicides}
- H10W 20/076: {in via holes or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices and methods of forming the same are provided. In one embodiments, a semiconductor device includes an n-type transistor region and a p-type transistor region. The n-type transistor region includes a first gate stack, a first gate spacer over sidewalls of the first gate stack, an n-type epitaxial feature in a source/drain (S/D) region of the n-type transistor region, and a first metal silicide layer over the n-type epitaxial feature. The p-type transistor region includes a second gate stack, a second gate spacer over sidewalls of the second gate stack, a p-type epitaxial feature in an S/D region of the p-type transistor region, a dopant-containing implant layer over the p-type epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant.

## Claims

### Claim 1

A semiconductor device, comprising:
an n-type transistor region including:
a first gate stack;
a first gate spacer over sidewalls of the first gate stack;
an n-type epitaxial feature in a source/drain (S/D) region of the n-type transistor region; and
a first metal silicide layer over the n-type epitaxial feature; and
a p-type transistor region including:
a second gate stack;
a second gate spacer over sidewalls of the second gate stack;
a p-type epitaxial feature in an S/D region of the p-type transistor region;
a dopant-containing implant layer over the p-type epitaxial feature, wherein the dopant-containing implant layer includes a metallic dopant; and
a second metal silicide layer over the dopant-containing implant layer,
wherein a top surface of the n-type epitaxial feature has a first concave profile, a top surface of the p-type epitaxial feature has a second concave profile, and a lowest point of the first concave profile is below a lowest point of the second concave profile.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the metallic dopant is gallium (Ga).

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the p-type epitaxial feature and the dopant-containing implant layer both include silicon germanium (SiGe).

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the n-type epitaxial feature is substantially free of the metallic dopant.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the dopant-containing implant layer further includes a non-metallic dopant.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the non-metallic dopant is boron (B).

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first and second metal silicide layers include different metallic elements.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the second metal silicide layer includes the metallic dopant and the first metal silicide layer is substantially free of the metallic dopant.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein a first vertical distance between a bottom surface of the first gate spacer and the lowest point of the first concave profile is greater than a second vertical distance between a bottom surface of the second gate spacer and the lowest point of the second concave profile.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the lowest point of the first concave profile is below the lowest point of the second concave profile for at least 5 nm.

### Claim 11

A semiconductor device, comprising:
a fin protruding from a substrate, the fin having a first source/drain (S/D) region, a second S/D region, and a channel region connecting the first and second S/D regions;
a gate structure over the channel region of the fin;
a first S/D feature comprising silicon germanium (SiGe) disposed in the first S/D region of the fin, wherein a top portion of the first S/D feature is doped with gallium (Ga) and a bottom portion of the first S/D feature is free of Ga;
a second S/D feature disposed in the second S/D region of the fin, wherein the second S/D feature is free of Ga, and wherein in cross-sectional views each along a lengthwise direction of the gate structure, a top surface of the first S/D feature is below a top surface of the second S/D feature;
a metal silicide layer over the top surface of the first S/D feature; and
an S/D contact disposed on the metal silicide layer and electrically coupled to the first S/D feature.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein in a cross-sectional view along a lengthwise direction of the fin, a top surface of the first S/D feature has a concave profile with a lowest point below a top surface of the fin.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the top portion of the first S/D feature is also doped with boron (B).

### Claim 14 (depends on 11)

The semiconductor device of claim 11, further comprising:
a gate spacer layer disposed on sidewalls of the gate structure;
a contact etch stop layer (CESL) disposed on sidewalls of the gate spacer layer; and
a protective dielectric layer interposing the CESL and the S/D contact.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein in a cross-sectional view along a lengthwise direction of the fin, the top surface of the first S/D feature has a concave profile, and the top surface of the second S/D feature is substantially flat.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein in the cross-sectional views each along the lengthwise direction of the gate structure, the top surface of the first S/D feature and the top surface of the second S/D feature each have a rhombus profile.

### Claim 17 (depends on 11)

The semiconductor device of claim 11, wherein the second S/D feature includes SiGe.

### Claim 18

A semiconductor device comprising:
an n-type FinFET region including:
a first gate stack;
a first gate spacer over sidewalls of the first gate stack;
an n-type epitaxial feature in a source/drain (S/D) region of the n-type FinFET region; and
a first metal silicide layer over the n-type epitaxial feature; and
a p-type FinFET region including:
a second gate stack;
a second gate spacer over sidewalls of the second gate stack;
a silicon germanium (SiGe) epitaxial feature in an S/D region of the p-type FinFET region, wherein a top portion of the SiGe epitaxial feature includes gallium (Ga); and
a second metal silicide layer over the top portion of the SiGe epitaxial feature,
wherein a top surface of the n-type epitaxial feature has a first concave profile, a top surface of the SiGe epitaxial feature has a second concave profile, and a lowest point of the first concave profile is below a lowest point of the second concave profile.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the SiGe epitaxial feature further includes boron (B).

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein a first vertical distance between a bottom surface of the first gate spacer and the lowest point of the first concave profile is greater than a second vertical distance between a bottom surface of the second gate spacer and the lowest point of the second concave profile.