# US 12,009,362 B2 · Method of making amphi-FET structure and method of designing

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- Number: US 12,009,362 B2
- Document ID: US12009362B2
- Status: Granted
- Kind: B2
- Application number: 18/360,539
- Filed: 2023-07-27
- Published: 2024-01-18
- Granted: 2024-06-11
- Earliest claimed: 2021-03-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Yu Lai; Chih-Liang Chen; Chi-Yu Lu; Shang-Syuan Ciou; Hui-Zhong Zhuang; Ching-Wei Tsai; Shang-Wen Chang
- Web page: https://patentgrep.com/patent/US12009362B2

## CPC

- H10D 88/101: {comprising components on opposite major surfaces of semiconductor substrates}
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/394: Routing (G06F30/396 takes precedence)
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 88/01: {Manufacture or treatment}
- H10P 14/3452: {Microstructure}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/427: {Power or ground buses}
- H10W 20/43: Layouts of interconnections
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of making a semiconductor device includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.

## Claims

### Claim 1

A method of making a semiconductor device, the method comprising:
forming a first active region on a first side of a substrate;
forming a first source/drain (S/D) electrode surrounding a first portion of the first active region;
forming an S/D connect via extending through the substrate;
flipping the substrate;
forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate; and
forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a first gate structure surrounding a second portion of the first active region;
forming a second gate structure surrounding a second portion of the second active region; and
forming a gate via extending through the substrate, wherein the gate via directly contacts both the first gate structure and the second gate structure.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the S/D connect via occurs prior to forming the first S/D electrode and prior to forming the second S/D electrode.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the S/D connect via occurs after forming the first S/D electrode.

### Claim 5 (depends on 1)

The method of claim 1, wherein flipping the substrate occurs prior to forming the S/D connect via.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the S/D connect via comprises forming the S/D connect via having a same width parallel to the first side of the substrate as a width of the first S/D electrode.

### Claim 7

A method of designing a semiconductor device, the method comprising:
receiving a layout of a device, wherein the device is designed to be formed on a single side of a substrate, and the layout comprises a plurality of routing tracks;
cutting the layout along a first direction, wherein the first direction is parallel to the plurality of routing tracks or perpendicular to the plurality of routing tracks;
dividing the cut layout into a first cell and a second cell based on a location of the cutting, wherein the first cell comprises a first gate structure, and the second cell comprises a second gate structure; and
inserting a gate via into the first cell or the second cell, wherein the gate via is positioned to directly connect to the first gate structure and to directly connect to the second gate structure.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first direction is parallel to the plurality of routing tracks.

### Claim 9 (depends on 7)

The method of claim 7, wherein the first direction is perpendicular to the plurality of routing tracks.

### Claim 10 (depends on 7)

The method of claim 7, further comprising:
positioning the first cell on a first side of the substrate; and
positioning the second cell on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate.

### Claim 11 (depends on 7)

The method of claim 7, further comprising inserting a source/drain (S/D) via into the first cell or the second cell, wherein the S/D via directly connects to a first S/D region in the first cell and directly connects to a second S/D region in the second cell.

### Claim 12 (depends on 7)

The method of claim 7, further comprising instructing fabrication tools to manufacture the semiconductor device following the inserting the gate via.

### Claim 13

A method of making a semiconductor device, the method comprising:
forming a first electrode surrounding a first portion of a first active region on a first side of a substrate;
forming a second electrode surrounding a second portion of a second active region on a second side of the substrate; and
forming a through substrate via extending through the substrate, wherein the through substrate via directly contacts both the first electrode and the second electrode.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the first electrode comprises forming a source/drain (S/D) electrode.

### Claim 15 (depends on 13)

The method of claim 13, wherein forming the first electrode comprises forming a gate electrode.

### Claim 16 (depends on 13)

The method of claim 13, wherein forming the through substrate via comprises forming the through substrate via having a same width, measured parallel to the first side of the substrate, as at least one of the first electrode or the second electrode.

### Claim 17 (depends on 13)

The method of claim 13, wherein forming the through substrate via comprises forming the through substrate via having a smaller width, measured parallel to the first side of the substrate, than both the first electrode and the second electrode.

### Claim 18 (depends on 13)

The method of claim 13, further comprising:
forming a third electrode surrounding a third portion of the first active region; and
forming a fourth electrode surrounding a fourth portion of the second active region.

### Claim 19 (depends on 18)

The method of claim 18, further comprising forming a second through substrate via extending through the substrate, wherein the second through substrate via directly connects to the third electrode and the fourth electrode.

### Claim 20 (depends on 19)

The method of claim 19, wherein forming the second through substrate via comprises forming the second through substrate via offset from the through substrate via in a first direction parallel to the first side of the substrate, and offset from the through substrate via in a second direction perpendicular to a longitudinal direction of the first active region.