# US 12,009,356 B2 · Integrated circuit and method of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,356 B2 - Document ID: US12009356B2 - Status: Granted - Kind: B2 - Application number: 18/190,703 - Filed: 2023-03-27 - Published: 2023-07-20 - Granted: 2024-06-11 - Earliest claimed: 2020-01-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chun-Yao Ku; Wen-Hao Chen; Kuan-Ting Chen; Ming-Tao Yu; Jyun-Hao Chang - Web page: https://patentgrep.com/patent/US12009356B2 ## CPC - H10D 89/10: Integrated device layouts - G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 62/121: {oriented parallel to substrates} - H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors} - H10K 30/83: comprising arrangements for extracting the current from the cell, e.g. metal finger grid systems to reduce the serial resistance of transparent electrodes - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/688: {Flexible insulating substrates} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/853: {comprising FinFETs} - H10D 84/975: {Wiring regions or routing} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A method of forming an integrated circuit includes placing a first and a second standard cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height. Placing the first standard cell layout design includes placing a first set of pin layout patterns on a first layout level over a first set of gridlines, extending in a first direction, and having a first width in a second direction. Placing the second standard cell layout design includes placing a second set of pin layout patterns on the first layout level over a second set of gridlines, extending in the first direction, and having a second width in the second direction. ## Claims ### Claim 1 A method of forming an integrated circuit, the method comprising: placing, by a processor, a first standard cell layout design of the integrated circuit on a layout design, the first standard cell layout design having a first height, the placing the first standard cell layout design includes: placing a first set of pin layout patterns on a first layout level and over a first set of gridlines, the first set of pin layout patterns extending in a first direction, and having a first width in a second direction different from the first direction; placing a second standard cell layout design of the integrated circuit adjacent to the first standard cell layout design, the second standard cell layout design having a second height different from the first height, the first height and the second height being in the second direction, the placing the second standard cell layout design includes: placing a second set of pin layout patterns on the first layout level and over a second set of gridlines, the second set of pin layout patterns extending in the first direction, and having a second width in the second direction, the second width being different from the first width; and manufacturing the integrated circuit based on at least the first standard cell layout design or the second standard cell layout design. ### Claim 2 (depends on 1) The method of claim 1, wherein the placing the first standard cell layout design of the integrated circuit, further includes: placing a first set of conductive feature layout patterns on a second layout level different from the first layout level, the first set of conductive feature layout patterns extending in the second direction, and overlapping at least the first set of pin layout patterns, and the placing the second standard cell layout design of the integrated circuit, further includes: placing a second set of conductive feature layout patterns and on the second layout level, the second set of conductive feature layout patterns extending in the second direction, and overlapping at least the second set of pin layout patterns. ### Claim 3 (depends on 2) The method of claim 2, wherein the placing the first standard cell layout design of the integrated circuit, further includes: placing a first set of via layout patterns between the first set of pin layout patterns and the first set of conductive feature layout patterns, the first set of via layout patterns having a first via width and a first via height; and the placing the second standard cell layout design of the integrated circuit, further includes: placing a second set of via layout patterns between the second set of pin layout patterns and the second set of conductive feature layout patterns, the second set of via layout patterns having a second via width different from the first via width or a second via height different from the first via height. ### Claim 4 (depends on 3) The method of claim 3, wherein the placing the first standard cell layout design of the integrated circuit, further includes: placing a third set of conductive feature layout patterns on a third layout level and over a third set of gridlines, the third set of conductive feature layout patterns extending in the first direction, and overlapping at least the first set of conductive feature layout patterns, the third layout level being different from the first layout level and the second layout level, and the placing the second standard cell layout design of the integrated circuit, further includes: placing a fourth set of conductive feature layout patterns on the third layout level and over a fourth set of gridlines, the fourth set of conductive feature layout patterns extending in the first direction, and overlapping at least the second set of conductive feature layout patterns. ### Claim 5 (depends on 4) The method of claim 4, wherein each gridline of the first set of gridlines is separated from an adjacent gridline of the first set of gridlines in the second direction by a first pitch of the first set of pin layout patterns; each gridline of the second set of gridlines is separated from an adjacent gridline of the second set of gridlines in the second direction by a second pitch of the second set of pin layout patterns, the second pitch being different from the first pitch; each gridline of the third set of gridlines is separated from an adjacent gridline of the third set of gridlines in the second direction by a third pitch of the third set of conductive feature layout patterns; and each gridline of the fourth set of gridlines is separated from an adjacent gridline of the fourth set of gridlines in the second direction by a fourth pitch of the fourth set of conductive feature layout patterns, the fourth pitch being different from the third pitch. ### Claim 6 (depends on 4) The method of claim 4, wherein the placing the first standard cell layout design of the integrated circuit, further includes: placing a third set of via layout patterns between the third set of conductive feature layout patterns and the first set of conductive feature layout patterns, the third set of via layout patterns having a third via width and a third via height; and the placing the second standard cell layout design of the integrated circuit, further includes: placing a fourth set of via layout patterns between the fourth set of conductive feature layout patterns and the second set of conductive feature layout patterns, the fourth set of via layout patterns having a fourth via width different from the third via width or a fourth via height different from the third via height. ### Claim 7 (depends on 4) The method of claim 4, wherein the placing the first standard cell layout design of the integrated circuit, further includes: placing a first set of active region layout patterns on a fourth layout level, the first set of active region layout patterns corresponding to fabricating a first set of active regions, the first set of active region layout patterns having a third width in the second direction, the fourth layout level being different from the first layout level, the second layout level and the third layout level; and the placing the second standard cell layout design of the integrated circuit, further includes: placing a second set of active region layout patterns on the fourth layout level, the second set of active region layout patterns corresponding to fabricating a second set of active regions, the second set of active region layout patterns having a fourth width in the second direction different from the third width. ### Claim 8 A method of forming an integrated circuit, the method comprising: placing, by a processor, a first standard cell layout design of the integrated circuit on a layout design, the first standard cell layout design having a first height, the placing the first standard cell layout design includes: placing a first set of pin layout patterns on a first layout level and over a first set of gridlines, the first set of pin layout patterns extending in a first direction, and having a first width in a second direction different from the first direction; placing a first set of gate layout patterns on a second layout level different from the first layout level, the first set of gate layout patterns extending in the second direction different from the first direction; placing a second standard cell layout design of the integrated circuit adjacent to the first standard cell layout design, the second standard cell layout design having a second height different from the first height, the first height and the second height being in the second direction, the placing the second standard cell layout design includes: placing a second set of pin layout patterns on the first layout level and over a second set of gridlines, the second set of pin layout patterns extending in the first direction, and having a second width in the second direction, the second width being different from the first width; and placing a second set of gate layout patterns on the second layout level, the second set of gate layout patterns extending in the second direction; and manufacturing the integrated circuit based on at least the first standard cell layout design or the second standard cell layout design. ### Claim 9 (depends on 8) The method of claim 8, wherein the placing the first standard cell layout design of the integrated circuit, further includes: placing a first set of conductive feature layout patterns on a third layout level different from the first layout level and the second layout level, the first set of conductive feature layout patterns extending in the second direction, and overlapping at least the first set of pin layout patterns, and the placing the second standard cell layout design of the integrated circuit, further includes: placing a second set of conductive feature layout patterns on the third layout level, the second set of conductive feature layout patterns extending in the second direction, and overlapping at least the second set of pin layout patterns. ### Claim 10 (depends on 9) The method of claim 9, wherein the placing the first standard cell layout design of the integrated circuit, further includes: placing a first set of via layout patterns between the first set of pin layout patterns and the first set of conductive feature layout patterns, the first set of via layout patterns having a first via width or a first via height; and the placing the second standard cell layout design of the integrated circuit, further includes: placing a second set of via layout patterns between the second set of pin layout patterns and the second set of conductive feature layout patterns, the second set of via layout patterns having a second via width different from the first via width or a second via height different from the first via height. ### Claim 11 (depends on 10) The method of claim 10, wherein the placing the first standard cell layout design of the integrated circuit, further includes: placing a third set of conductive feature layout patterns on a fourth layout level and over a third set of gridlines, the third set of conductive feature layout patterns extending in the first direction, and overlapping at least the first set of conductive feature layout patterns and the first set of gate layout patterns, the fourth layout level being different from the first layout level, the second layout level and the third layout level, and the placing the second standard cell layout design of the integrated circuit, further includes: placing a fourth set of conductive feature layout patterns on the fourth layout level and over a fourth set of gridlines, the fourth set of conductive feature layout patterns extending in the first direction, and overlapping at least the second set of conductive feature layout patterns and the second set of gate layout patterns. ### Claim 12 (depends on 11) The method of claim 11, wherein each gridline of the first set of gridlines is separated from an adjacent gridline of the first set of gridlines in the second direction by a first pitch; each gridline of the second set of gridlines is separated from an adjacent gridline of the second set of gridlines in the second direction by a second pitch, the second pitch being different from the first pitch; each gridline of the third set of gridlines is separated from an adjacent gridline of the third set of gridlines in the second direction by a third pitch; and each gridline of the fourth set of gridlines is separated from an adjacent gridline of the fourth set of gridlines in the second direction by a fourth pitch, the fourth pitch being different from the third pitch. ### Claim 13 (depends on 11) The method of claim 11, wherein the placing the first standard cell layout design of the integrated circuit, further includes: placing a third set of via layout patterns between the third set of conductive feature layout patterns and the first set of conductive feature layout patterns, the third set of via layout patterns having a third via width or a third via height; and the placing the second standard cell layout design of the integrated circuit, further includes: placing a fourth set of via layout patterns between the fourth set of conductive feature layout patterns and the second set of conductive feature layout patterns, the fourth set of via layout patterns having a fourth via width different from the third via width or a fourth via height different from the third via height. ### Claim 14 (depends on 11) The method of claim 11, wherein the placing the first standard cell layout design of the integrated circuit, further includes: placing a first set of active region layout patterns on a fifth layout level, the first set of active region layout patterns corresponding to fabricating a first set of active regions, the first set of active region layout patterns having a third width in the second direction, the fifth layout level being different from the first layout level, the second layout level, the third layout level and the fourth layout level; and the placing the second standard cell layout design of the integrated circuit, further includes: placing a second set of active region layout patterns on the fifth layout level, the second set of active region layout patterns corresponding to fabricating a second set of active regions, the second set of active region layout patterns having a fourth width in the second direction different from the third width. ### Claim 15 A system for manufacturing an integrated circuit, the system comprising: a non-transitory computer readable medium configured to store non-transitory instructions; and a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the non-transitory instructions comprising: placing a first standard cell layout design of the integrated circuit on a layout design, the first standard cell layout design having a first height, the placing the first standard cell layout design includes: placing a first set of pin layout patterns on a first layout level and over a first set of gridlines, the first set of pin layout patterns extending in a first direction, and having a first width in a second direction different from the first direction; placing a second standard cell layout design of the integrated circuit adjacent to the first standard cell layout design, the second standard cell layout design having a second height different from the first height, the first height and the second height being in the second direction, the placing the second standard cell layout design includes: placing a second set of pin layout patterns on the first layout level and over a second set of gridlines, the second set of pin layout patterns extending in the first direction, and having a second width in the second direction, the second width being different from the first width. ### Claim 16 (depends on 15) The system of claim 15, wherein the processor configured to execute the non-transitory instructions comprising: the placing the first standard cell layout design of the integrated circuit comprises the processor being further configured to execute the non-transitory instructions further comprising: placing a first set of conductive feature layout patterns on a second layout level different from the first layout level, the first set of conductive feature layout patterns extending in the second direction, and overlapping at least the first set of pin layout patterns, and the placing the second standard cell layout design of the integrated circuit comprises the processor being further configured to execute the non-transitory instructions further comprising: placing a second set of conductive feature layout patterns and on the second layout level, the second set of conductive feature layout patterns extending in the second direction, and overlapping at least the second set of pin layout patterns. ### Claim 17 (depends on 16) The system of claim 16, wherein the processor configured to execute the non-transitory instructions comprising: the placing the first standard cell layout design of the integrated circuit comprises the processor being further configured to execute the non-transitory instructions further comprising: placing a first set of via layout patterns between the first set of pin layout patterns and the first set of conductive feature layout patterns, the first set of via layout patterns having a first via width and a first via height; and the placing the second standard cell layout design of the integrated circuit comprises the processor being further configured to execute the non-transitory instructions further comprising: placing a second set of via layout patterns between the second set of pin layout patterns and the second set of conductive feature layout patterns, the second set of via layout patterns having a second via width different from the first via width or a second via height different from the first via height. ### Claim 18 (depends on 17) The system of claim 17, wherein the processor configured to execute the non-transitory instructions comprising: the placing the first standard cell layout design of the integrated circuit comprises the processor being further configured to execute the non-transitory instructions further comprising: placing a third set of conductive feature layout patterns on a third layout level and over a third set of gridlines, the third set of conductive feature layout patterns extending in the first direction, and overlapping at least the first set of conductive feature layout patterns, the third layout level being different from the first layout level and the second layout level, and the placing the second standard cell layout design of the integrated circuit comprises the processor being further configured to execute the non-transitory instructions further comprising: placing a fourth set of conductive feature layout patterns on the third layout level and over a fourth set of gridlines, the fourth set of conductive feature layout patterns extending in the first direction, and overlapping at least the second set of conductive feature layout patterns. ### Claim 19 (depends on 18) The system of claim 18, wherein each gridline of the first set of gridlines is separated from an adjacent gridline of the first set of gridlines in the second direction by a first pitch of the first set of pin layout patterns; each gridline of the second set of gridlines is separated from an adjacent gridline of the second set of gridlines in the second direction by a second pitch of the second set of pin layout patterns, the second pitch being different from the first pitch; each gridline of the third set of gridlines is separated from an adjacent gridline of the third set of gridlines in the second direction by a third pitch of the third set of conductive feature layout patterns; and each gridline of the fourth set of gridlines is separated from an adjacent gridline of the fourth set of gridlines in the second direction by a fourth pitch of the fourth set of conductive feature layout patterns, the fourth pitch being different from the third pitch. ### Claim 20 (depends on 18) The system of claim 18, wherein the processor configured to execute the non-transitory instructions comprising: the placing the first standard cell layout design of the integrated circuit comprises the processor being further configured to execute the non-transitory instructions further comprising: placing a third set of via layout patterns between the third set of conductive feature layout patterns and the first set of conductive feature layout patterns, the third set of via layout patterns having a third via width and a third via height; and the placing the second standard cell layout design of the integrated circuit comprises the processor being further configured to execute the non-transitory instructions further comprising: placing a fourth set of via layout patterns between the fourth set of conductive feature layout patterns and the second set of conductive feature layout patterns, the fourth set of via layout patterns having a fourth via width different from the third via width or a fourth via height different from the third via height.