# US 12,009,354 B2 · SSD wafer device and method of manufacturing same

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- Number: US 12,009,354 B2
- Document ID: US12009354B2
- Status: Granted
- Kind: B2
- Application number: 17/547,455
- Filed: 2021-12-10
- Published: 2023-06-15
- Granted: 2024-06-11
- Earliest claimed: 2021-12-10
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Ken Funaki
- Web page: https://patentgrep.com/patent/US12009354B2

## CPC

- H10W 72/90: Bond pads, in general
- H10W 90/00: Package configurations
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/692: Ceramics or glasses
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A solid state drive (SSD) wafer device includes first and second semiconductor wafers coupled together. The first wafer may include a number of memory dies with die bond pads, and the second wafer may include a number of electrical interconnects, each including first and second terminals at opposed ends of the electrical interconnect. When the wafers are bonded together, the first terminals of the second wafer are bonded to the die bond pads of the memory dies of the first wafer. The second terminals are left exposed to couple with an SSD controller, which controls the transfer of data and signals between the memory dies of the first wafer and a host device such as a server in a datacenter.

## Claims

### Claim 1

A solid state drive (SSD) wafer device, comprising:
a first semiconductor wafer comprising first and second major surfaces, a plurality of memory dies, each memory die of the plurality of memory dies comprising a plurality of bond pads at the first major surface, and one or more cutouts; and
a second semiconductor wafer comprising third and fourth major surfaces, and a plurality of electrical interconnects, each electrical interconnect comprising a first terminal at the third major surface, at a first end of the electrical interconnect, and a second terminal at the third major surface, at a second end of the electrical interconnect opposite the first end, the second terminal of each of the electrical interconnects configured to transfer signals between the second semiconductor wafer and an external device;
wherein the first major surface of the first semiconductor wafer is coupled to the third major surface of the second semiconductor wafer, with the first terminal of each of the plurality of electrical interconnects bonded to a die bond pad of the plurality of die bond pads and the second terminal of each of the plurality of electrical interconnects positioned in the one or more cutouts.

### Claim 2 (depends on 1)

The SSD wafer device of claim 1, wherein the one or more cutouts comprise a plurality of cutouts are positioned around a periphery of the first semiconductor wafer.

### Claim 3 (depends on 1)

The SSD wafer device of claim 1, further comprising one or more SSD controllers electrically coupled to the second terminals of the plurality of electrical interconnects.

### Claim 4 (depends on 3)

The SSD wafer device of claim 3, wherein at least one of the one or more SSD controllers is physically positioned within the one or more cutouts.

### Claim 5 (depends on 4)

The SSD wafer device of claim 4, wherein the at least one SSD controller is flip-chip bonded to the second terminal of at least some of the plurality of electrical interconnects.

### Claim 6 (depends on 1)

The SSD wafer device of claim 1, further comprising:
a plurality of signal/data connectors directly coupled to the second terminals of the plurality of electrical interconnects; and
an SSD controller coupled to the plurality of signal/data connectors to transfer one or both of signals and data to and from the second terminals of the plurality of electrical interconnects.

### Claim 7 (depends on 6)

The SSD wafer device of claim 6, wherein the SSD controller comprises a master SSD controller, and the plurality of signal/data connectors comprise SSD controllers coupled to the master SSD controller.

### Claim 8

A solid state drive (SSD) wafer device, comprising:
a first semiconductor wafer comprising first and second major surfaces, a plurality of memory dies, each memory die comprising a plurality of bond pads at the first major surface, and one or more cutouts;
a second semiconductor wafer bonded to the first semiconductor wafer, the second semiconductor wafer comprising third and fourth major surfaces, and a plurality of electrical interconnects, each electrical interconnect comprising a first terminal at the third major surface, at a first end of the electrical interconnect, and a second terminal at the third major surface, at a second end of the electrical interconnect opposite the first end, the first terminal of each of the plurality of electrical interconnects bonded to a die bond pad of the plurality of die bond pads; and
one or more SSD controllers positioned in the one or more cutouts and electrically coupled to the second terminals of the plurality of electrical interconnects.

### Claim 9 (depends on 8)

The SSD wafer device of claim 8, wherein at least one SSD controller of the one or more SSD controllers comprises bond pads that are directly coupled to the second terminals of the plurality of electrical interconnects.

### Claim 10 (depends on 8)

The SSD wafer device of claim 8, wherein the one or more cutouts comprise at least one cutout at a periphery of the first semiconductor wafer.

### Claim 11 (depends on 10)

The SSD wafer device of claim 10, wherein the second terminals of the plurality of electrical interconnects terminate at the third major surface of the second semiconductor wafer at positions corresponding to the at least one cutout when the first and second semiconductor wafer are coupled together.

### Claim 12

A solid state drive (SSD) wafer device, comprising:
a first semiconductor wafer comprising first and second major surfaces, a plurality of NAND dies, each NAND die of the plurality of NAND dies comprising a plurality of bond pads at the first major surface, and one or more cutouts;
a second semiconductor wafer coupled to the first semiconductor wafer, the second semiconductor wafer comprising third and fourth major surfaces, and electrical interconnect means comprising first ends at the third major surface and second ends at the third major surface;
wherein the first and second wafers are bonded together such that the first ends of the electrical interconnect means are electrically coupled to the die bond pads of the plurality of die bond pads and the second ends of the electrical interconnect means positioned within the one or more cutouts.