# US 12,009,352 B2 · Fabricating wafers with electrical contacts on a surface parallel to an active surface

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- Number: US 12,009,352 B2
- Document ID: US12009352B2
- Status: Granted
- Kind: B2
- Application number: 17/419,385
- Filed: 2020-09-16
- Published: 2022-07-07
- Granted: 2024-06-11
- Earliest claimed: 2019-09-26
- Assignees: Illumina, Inc.
- Applicants: Illumina, Inc.
- Inventors: Arvin Emadi; Jon Aday; Ali Agah; Arnaud Rival
- Web page: https://patentgrep.com/patent/US12009352B2

## CPC

- G01N 21/05: Flow-through cuvettes (G01N21/09 takes precedence; handling fluid samples G01N1/10)
- H10W 90/00: Package configurations
- G01N 21/6454: {using an integrated detector array}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- G01N 2021/6482: {Sample cells, cuvettes}
- H10P 72/0428: {Apparatus for mechanical treatment or grinding or cutting}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/655: Fan-out layouts
- H10W 72/0198: {batch processes}
- H10W 72/221: {Structures or relative sizes}
- G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided herein include various examples of a method for manufacturing aspects of an apparatus, a sensor system. The method may include obtaining a first carrier bonded to an upper surface of the silicon wafer. This wafer includes through silicon vias (TSVs) extended through openings in a passivation stack, with electrical contacts coupled to portions of the TSVs exposed through these openings. The method may include de-bonding the first carrier from the upper surface of the silicon wafer. The method may include dicing the silicon wafer into subsections comprising dies.

## Claims

### Claim 1

A method comprising:
obtaining a first carrier bonded to an upper surface of the silicon wafer, wherein one or more through silicon vias are extended through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below a bottom surface of the silicon wafer, wherein a portion of each of the one or more through silicon vias is exposed through an opening of one or more openings in the passivation stack, wherein each exposed portion is coupled to one or more electrical contacts;
de-bonding the first carrier from the upper surface of the silicon wafer; and
dicing the silicon wafer into subsections comprising dies, such that each die comprises a portion of the upper surface of the silicon wafer, the portion of the upper surface of the silicon wafer comprising an active surface, at least one through silicon via of the one or more through silicon vias, and at least one electrical contact of the one or more electrical contacts on a second surface of the die, the second surface of the die parallel to the active surface.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming fan-out regions, the forming comprising:
coupling the active surfaces of the dies to a fan-out carrier, the coupling creating a first space adjacent to a first edge of each active surface of each die and a second space adjacent to a second edge of each active surface of each die;
forming a molding layer by depositing mold on the second surfaces of the dies and in each first space and each second space to form the molding layer over the fan-out carrier; and
polishing a top surface of the molding layer such that the at least one electrical contact of the one or more electrical contacts on the second surface of each die and the polished top surface of the molding layer form a contiguous surface.

### Claim 3 (depends on 2)

The method of claim 2, wherein the contiguous surface comprises flat electrical contacts of equal height and thickness.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
forming a metallization layer by coating metal on the contiguous surface in a pattern.

### Claim 5 (depends on 4)

The method of claim 4, wherein the metallization layer comprises a layer selected from the group consisting of: a fan-out redistribution layer based on the pattern distributing additional electrical contacts at locations different from locations of the at least one electrical contact of the one or more electrical contacts on the second surface of each die, and an under bump layer, based on the pattern distributing additional electrical contacts at locations of the at least one electrical contact of the one or more electrical contacts on the second surface of each die.

### Claim 6 (depends on 4)

The method of claim 4, wherein coating the metal on the contiguous surface comprises:
utilizing a photolithography technique to create the pattern;
electroplating the pattern, wherein the electroplating comprises depositing on the one or more openings, wherein the one or more openings comprise photoresist; and
stripping away the photoresist to reveal the metallization layer.

### Claim 7 (depends on 4)

The method of claim 4, further comprising:
depositing an electrical short prevention passivation layer on the metallization layer; and
utilizing photolithography to open the electrical short prevention passivation layer at one or more locations to from electrical connection pads to the metallization layer.

### Claim 8 (depends on 7)

The method of claim 7, further comprising, releasing the fan-out carrier to expose an active device surface comprising the active surfaces of the dies and surfaces of the first spaces and the second spaces contiguous with the active surfaces, the releasing comprising:
attaching a second carrier to the electrical short prevention passivation layer with an adhesive material; and
de-coupling the fan-out carrier from the active surfaces of the dies utilizing a technique selected from the group consisting of: applying mechanical pressure, heating the fan-out carrier, and applying a solvent.

### Claim 9 (depends on 7)

The method of claim 7, further comprising:
preparing the active device surface to act as a sensor, the preparing comprising:
washing the active device surface; and
processing the active device surface.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a fluidic flow channel over the active device surface, comprising:
attaching one or more lids to a portion of the mold to form the fluidic flow channel between the active device surface and the one or more lids; and
removing the second carrier from the electrical short prevention passivation layer to create a resultant structure.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
dicing the resultant structure into sub-structures, wherein each substructure comprises at least one die and at least one lid.

### Claim 12 (depends on 2)

The method of claim 2, further comprising:
forming a new passivation layer on the contiguous surface to planarize the contiguous surface;
forming openings in the new passivation layer to expose the at least one electrical contact of the one or more electrical contacts on the second surface of each die; and
forming a metallization layer by coating metal on the new passivation layer in a pattern.

### Claim 13 (depends on 2)

The method of claim 2, wherein coupling the active surfaces of the dies to the fan-out carrier comprises forming a temporary bonding layer between the active surfaces and the fan-out carrier, wherein the temporary bonding layer protects the active surfaces during the forming of the fan-out regions.

### Claim 14 (depends on 2)

The method of claim 2, wherein forming the molding layer further comprises curing the mold to attain mechanical stability, and wherein the molding layer is deposited to reach a height greater than a height of the at least one electrical contact on the second surface of each die.

### Claim 15 (depends on 1)

The method of claim 1, wherein the passivation stack comprises a metallization layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the metallization layer comprises a redistribution layer.

### Claim 17 (depends on 1)

The method of claim 1, wherein the obtaining comprises fabricating the one or more electrical contacts on the one or more openings in the passivation stack.

### Claim 18 (depends on 1)

The method of claim 1, further comprising:
prior to dicing the silicon wafer into subsections, placing the silicon wafer on a second carrier, such that the second carrier is coupled to the passivation stack;
prior to forming fan-out regions, releasing the second carrier from the silicon wafer.

### Claim 19

A method comprising:
obtaining a first carrier bonded to an upper surface of the silicon wafer, wherein one or more through silicon vias are extended through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below a bottom surface of the silicon wafer, wherein a portion of each of the one or more through silicon vias is exposed through an opening of one or more openings in the passivation stack;
fabricating one or more pillar bumps on the openings in the passivation stack;
de-bonding the first carrier from the upper surface of the silicon wafer; and
dicing the silicon wafer into subsections comprising dies.

### Claim 20

A method comprising:
obtaining a first carrier bonded to an upper surface of the silicon wafer, wherein one or more through silicon vias are extended through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below a bottom surface of the silicon wafer, wherein a portion of each of the one or more through silicon vias is exposed through an opening of one or more openings in the passivation stack, wherein one or more electrical contacts are disposed on the one or more openings in the passivation stack;
de-bonding the first carrier from the upper surface of the silicon wafer; and
dicing the silicon wafer into subsections comprising dies.