# US 12,009,350 B2 · Semiconductor package and method of fabricating the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,009,350 B2
- Document ID: US12009350B2
- Status: Granted
- Kind: B2
- Application number: 18/130,760
- Filed: 2023-04-04
- Published: 2023-08-03
- Granted: 2024-06-11
- Earliest claimed: 2018-09-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kyoung Lim Suk; Seokhyun Lee
- Web page: https://patentgrep.com/patent/US12009350B2

## CPC

- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/652: Cross-sectional shapes
- H10W 70/655: Fan-out layouts
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

## Claims

### Claim 1

A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder ball on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
a first insulating layer;
a redistribution pattern including a via portion in the first insulating layer and an interconnection portion connected to the via portion, the interconnection portion disposed on the first insulating layer;
a seed pattern covering a bottom surface and a side surface of the via portion and extending to a lower surface of the interconnection portion; and
a second insulating layer on the first insulating layer, the second insulating layer covering side surfaces of the interconnection portion,
wherein the seed pattern does not cover the side surfaces of the interconnection portion,
wherein the seed pattern is provided between the via portion and the solder ball, and
wherein a lowermost surface of the seed pattern is coplanar with a bottom surface of the first insulating layer.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein a bottom surface of the first insulating layer is exposed to an outside of the redistribution substrate,
wherein a maximum distance between the bottom surface of the first insulating layer and an upper surface of the interconnection portion ranges from 100% to 120% of a minimum distance between the bottom surface of the first insulating layer and the upper surface of the interconnection portion.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein an upper surface of the redistribution pattern has a surface roughness of 0.01 μm to 0.4 μm.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the interconnection portion has a width greater than that of the via portion.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the solder ball is electrically connected to the semiconductor chip through the redistribution pattern.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, further comprising a molding layer covering the semiconductor chip and provided on the top surface of the redistribution substrate,
wherein a sidewall of the molding layer is aligned with a sidewall of the redistribution substrate.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, further comprising a bump between the top surface of the redistribution substrate and a chip pad of the semiconductor chip,
wherein the semiconductor chip is electrically connected to the redistribution pattern through the bump.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein a top surface of the second insulating layer is substantially coplanar with a top surface of the interconnection portion.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein a width of one surface of the interconnection portion ranges from 100% to 120% of a width of another surface of the interconnection portion.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein the one surface and the other surface of the interconnection portion are opposite to each other, and
wherein one of the one surface and the other surface of the interconnection portion is the lower surface of the interconnection portion.

### Claim 11

A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder ball on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
a first redistribution pattern including a first via portion on the solder ball and a first interconnection portion connected to the first via portion;
a first seed pattern covering a bottom surface and a side surface of the first via portion and extending to a lower surface of the first interconnection portion;
a first insulating layer on an upper surface of the first interconnection portion;
a second redistribution pattern on the first redistribution pattern, the second redistribution pattern including a second via portion in the first insulating layer and a second interconnection portion connected to the second via portion;
a second seed pattern covering a bottom surface and a side surface of the second via portion and extending to a lower surface of the second interconnection portion; and
a second insulating layer on the first insulating layer, the second insulating layer covering side surfaces of the second interconnection portion,
wherein the first seed pattern does not cover side surfaces of the first interconnection portion,
wherein the second seed pattern does not cover the side surfaces of the second interconnection portion,
wherein the first seed pattern is provided between the first via portion and the solder ball,
wherein a top surface of the second insulating layer is substantially coplanar with a top surface of the second interconnection portion, and
wherein the solder ball is adjacent to a bottom surface of the first seed pattern.

### Claim 12 (depends on 11)

The semiconductor package of claim 11, wherein a maximum distance between a bottom surface of the redistribution substrate and an upper surface of the second redistribution pattern ranges from 100% to 120% of a minimum distance between the bottom surface of the redistribution substrate and the upper surface of the second redistribution pattern.

### Claim 13 (depends on 11)

The semiconductor package of claim 11, wherein a width of the second via portion is smaller than a width of the second interconnection portion.

### Claim 14 (depends on 11)

The semiconductor package of claim 11, wherein an upper surface of the second interconnection portion has a surface roughness of 0.01 μm to 0.4 μm.

### Claim 15 (depends on 11)

The semiconductor package of claim 11, wherein a width of one surface of the second interconnection portion ranges from 100% to 120% of a width of another surface of the second interconnection portion.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein the one surface and the other surface of the second interconnection portion are opposite to each other, and
wherein one of the one surface and the other surface of the second interconnection portion is the lower surface of the second interconnection portion.

### Claim 17

A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder ball on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
a first insulating layer;
a first redistribution pattern including a first via portion in the first insulating layer and a first interconnection portion connected to the first via portion, the first interconnection portion disposed on the first insulating layer;
a first seed pattern covering a bottom surface and a side surface of the first via portion and extending to a lower surface of the first interconnection portion;
a second insulating layer on the first insulating layer, the second insulating layer covering side surfaces of the first interconnection portion and a side surface of the first seed pattern,
a third insulating layer on an upper surface of the first interconnection portion;
a second redistribution pattern on the first redistribution pattern, the second redistribution pattern including a second via portion in the third insulating layer and a second interconnection portion connected to the second via portion;
a second seed pattern covering a bottom surface and a side surface of the second via portion and extending to a lower surface of the second interconnection portion; and
a fourth insulating layer on the third insulating layer, the fourth insulating layer covering side surfaces of the second interconnection portion and a side surface of the second seed pattern,
wherein the first seed pattern does not cover the side surfaces of the first interconnection portion,
wherein the second seed pattern does not cover the side surfaces of the second interconnection portion,
wherein the first seed pattern is provided between the first via portion and the solder ball, and
wherein the solder ball is adjacent to a bottom surface of the first seed pattern.

### Claim 18 (depends on 17)

The semiconductor package of claim 17, wherein a width of the first via portion is smaller than a width of the first interconnection portion,
wherein a width of the second via portion is smaller than a width of the second interconnection portion.

### Claim 19 (depends on 17)

The semiconductor package of claim 17, wherein a width of one surface of the first interconnection portion ranges from 100% to 120% of a width of another surface of the first interconnection portion,
wherein a width of one surface of the second interconnection portion ranges from 100% to 120% of a width of another surface of the second interconnection portion.